Rianta Releases AES Crypto and HMAC Acceleration ASIC IP Cores

AES/HMAC Security Acceleration IP for Applications such as CXL IDE, IPsec, Storage

Ottawa, Canada, December 21, 2020 - Rianta Solutions Inc, a leading supplier of high quality ASIC IP Cores for Ethernet, Security and Deep Learning announces a new family of AES bulk encryption and HMAC acceleration IP cores targeting ASIC and SoC devices for Applications such as CXL IDE, IPsec, and Storage.

The Rianta AES / HMAC Crypto Acceleration offering is a portfolio of best-in-class cryptographic acceleration IP cores that are highly scalable implementations capable of handling intensive throughput up to 1.6Tbps.

The expanded Security Acceleration IP family includes AES-GCM, AES-XTS, HMAC-SHA2, HMAC-SHA3 IP cores that are ideally suited for IDE , Storage, DRAM, IPSec, MACsec, or other high performance bulk encryption applications requiring confidentiality and authentication.

Rianta’s RS_AES_GCM cores meet both MACsec and IDE requirements, while the combination of Rianta’s RS_AES_XTS and RS_AES_HMAC cores provides a powerful security solution for a variety of storage applications.

“The distributed and disaggregated nature of data centers workloads is driving the demand to encrypt and authenticate all data across all interconnect paths.” said Richard deBoer, CEO of Rianta. “Rianta’s suite of cryptographic and authentication acceleration IP is ideally suited to secure these interconnects.”

Rianta’s IP cores are implemented in System Verilog and are available with an extensive UVM verification environment for integration into subsystem and full-chip verification environments.

High Level Features for RS_AES_GCM

• Supports up to 1.6 Tbps of throughput
• Supports the following ciphers:
  • AES-GCM-128 and AES-GCM-256
  • AES-CTR-128 and AES-CTR-256
  • GMAC
• Fully parameterized, pipelined and channelized
• 128-bit IV, 128-bit and 256-bit keys
• Supports variable number of AAD and TEXT blocks
• AES-GCM vs AES-CTR and KeyLen selectable on per packet basis
• Fixed, low-latency operation
• Supports multi-packet chaining (fragmentation) in GCM mode (useful for TLS record processing)

High Level Features for RS_AES_XTS

• Supports up to 1.6 Tbps of throughput
• XTS-AES-256, and XTS-AES-512
• Fully parameterized, pipelined and channelized
• Supports up to 8192 interleaved channels/contexts
• Separate Tweak/Key interface with Key Store to minimize transformation latency
• Supports low latency and high-rep rate modes
• CipherText Stealing (CTS) at full line bandwidth

High Level Features for RS_HMAC_SHA2, RS_HMAC_SHA3

• Supports up to 25G BW in SHA2 and 100G BW in SHA3 modes
• Fully channelized, parameterized architecture with configurable number of rounds per cycle
• Dual use mode with HMAC bypass function per message
• Supports message fragmentation and interleaving
• Digest size (SHA2/3), b_type (SHA3), and c_size (SHA3) selectable per message

The following products are available:

About Rianta Solutions Inc.

Rianta Solutions Inc. offers high quality IP Cores, Verification IP Products and Engineering Design and Verification Services for ASICs, SoC and ASSP designs to the world's largest semiconductor and hardware equipment vendors.

Rianta’s IP Cores and Verification IP are for Ethernet, Security and Deep Learning Acceleration applications. Our IP products and Engineering services are optimized for Datacenter Infrastructure, Communications Infrastructure and Automotive Networking. For more information on Rianta IP Cores please Visit : https://www.riantasolutions.com/ip-cores

For more information, please visit: https://www.riantasolutions.com

Rianta Releases AES Crypto and HMAC Acceleration ASIC IP Cores