SEGGER introduces new Open Flashloader for direct programming of any RISC-V system
January 12, 2021 -- SEGGER just released a new Open Flashloader for RISC-V systems. The template, which can be adjusted to fit any RISC-V system, allows engineers to write flash loaders which fit into just 2kB of RAM.
This enables J-Link debug probes to download directly and easily into the flash memory of a RISC-V Microcontroller or SoC. At the same time it provides a solution for mass production programming using the Flasher series of flash programmers.
Ad |
RISC-V-based SoC template ![]() Low-power 32-bit RISC-V processor ![]() Compact, efficient 64-bit RISC-V processor with 5-stage pipeline ![]() |
These flash loaders work with any software supporting J-Link, from simple command line programs such as J-Link Commander, to debuggers such as GDB or SEGGER's Ozone, or more production-oriented utilities such as J-Flash, and development tools such as Embedded Studio. The J-Link GDB Server enables the use of GDB, Eclipse and any debugger supporting the GDB protocol.
When debugging with the J-Link Plus, Ultra+ or PRO models, an unlimited number of breakpoints in flash memory are available.
“We are seeing RISC-V gain more and more traction in the market, especially in China,” says Rolf Segger, founder of SEGGER. “Now even very small RISC-V systems can be programmed at blistering speed using SEGGER J-Link and Flasher. I think the convenience and performance of J-Link is industry leading, boosting developer productivity. With J-Link debugging and flash programming, a complete ecosystem of tools is available".”
Any qualified engineer can write a flash loader for J-Link and RISC-V, usually within a day or two. SEGGER also offers the service of writing flash loaders for particular devices where desired.
Proven flash loaders can be added to the J-Link software, so that they will simply work out of the box.
More information on J-Link Flasher loaders can be found here:
|
Related News
- Breker Verification Systems and Codasip Announce Cooperation to Drive Open, Commercial-Grade RISC-V SoC Verification Processes
- SEGGER adds 64-bit RISC-V support to Embedded Studio
- Haawking licenses SEGGER's emRun for RISC-V
- proteanTecs Joins the Open Compute Project (OCP), and Introduces First-Ever UCT Monitoring System for Field-Deployed Electronics
- RV64X: A Free, Open Source GPU for RISC-V
Breaking News
- Credo Launches Comprehensive Family of 112G PAM4 SerDes IP for TSMC N5 and N4 Process Technologies
- Alphawave IP is officially 5.0 certified on the PCI-SIG Integrator's List
- BrainChip Empowers Next Generation of Technology Innovators with Launch of the University AI Accelerator Program
- QuickLogic Reports Fiscal 2022 Second Quarter Results
- Efinix Low Power, Small Footprint FPGA Selected for SPRESENSE Development Platform
Most Popular
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |