New Cadence Allegro X Design Platform Revolutionizes System Design
Allegro X Platform Offers Unparalleled Integration and Technology Across Multiple Engineering Domains, Delivering Up to 4X Productivity Improvements over Traditional Design Tools
SAN JOSE, Calif. -- June 8, 2021 -- Cadence Design Systems, Inc. (Nasdaq: CDNS) today debuted the Cadence® Allegro® X Design Platform, the industry’s first engineering platform for system design that unifies schematic, layout, analysis, design collaboration and data management. Built upon proven Allegro and OrCAD® core technology, the new Allegro X platform revolutionizes and streamlines the system design process for engineers—offering unparalleled collaboration across all engineering disciplines, integration with best-in-class Cadence signoff-level simulation and analysis products, and greater layout performance.
Engineers today increasingly must design and collaborate across multiple domains, including electromagnetic (EM), thermal, signal and power integrity (SI/PI), and logical/physical implementation. The Allegro X platform’s simplified user interaction model delivers quick technology access and immediate value for novice and expert users. By minimizing iterations and providing access to both the logical and physical domains simultaneously with concurrent collaboration capabilities across schematic, layout and analysis activities, the Allegro X platform reduces the time and effort to complete the design of complex systems by up to 4X compared to legacy design tools.
The Allegro X platform leverages a hybrid cloud solution that provides scalable compute resources and full technology access while reducing deployment footprints and complexity. With the Allegro X platform, engineers can now deliver high-quality designs with access to the Cadence Clarity™ 3D Solver, Celsius™ Thermal Solver, Sigrity™ technology and PSpice® for simulation and analysis, Allegro Pulse for design data management, and interoperability with the AWR® Microwave Office® RF design flow.
The Allegro X platform delivers significant improvement in design throughput and performance. By leveraging GPU technology in combination with core architectural optimization, Allegro X performance is accelerated across a wide range of operations. In addition, the Allegro X platform utilizes cloud resources to synthesize full or partial PCB designs. Innovative machine learning (ML) techniques concurrently optimize the design for manufacturing, SI and PI requirements while designing the power delivery network (PDN), device placement and signal interconnect as specified by the system architect/electrical engineer.
“The Allegro X platform establishes a unified engineering platform, boosting overall design team productivity up to 4X. Engineers now have a framework for logical and physical design, in 2D or 3D, single- or multi-board, that allows them to optimize resources even on the most complex 5G designs, enabled by interoperability with the AWR Microwave Office RF design flow,” said Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group at Cadence. “Cadence R&D has been working diligently with academia and industry partners on groundbreaking, analysis-driven PCB synthesis that significantly enhances design productivity.”
“Harnessing the power of accelerated computing by using NVIDIA GPUs enables Cadence’s Allegro X platform to boost performance up to 20X for interactive operations,” said Greg Bodi, director of PCB layout engineering at NVIDIA. “This performance improvement delivers our engineers immediate canvas responsiveness and acceleration when 2D rendering complex boards during the design phase.”
“Multi-objective optimization is a challenging problem and I am pleased that MIT students and alumni have made significant progress working inside Cadence on novel ML solutions towards the synthesis of difficult PCB designs. The resulting system will not only benefit MIT, but will also significantly improve productivity in the PCB community at large,” said Dr. Tomas Palacios, professor of electrical engineering and computer science at MIT.
The Allegro X platform supports Cadence’s Intelligent System Design™ strategy, which enables customers to accelerate system innovation. Customers can learn more at www.cadence.com/go/allegrox. The Allegro X Design Platform will be available for general release in the fourth quarter of 2021.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications, including consumer, hyperscale computing, 5G communications, automotive, mobile, aerospace, industrial and healthcare. For seven years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.
Search Silicon IP
Cadence Hot IP
- Cadence Revolutionizes Verification Productivity with the Verisium AI-Driven Verification Platform
- Cadence Revolutionizes System Design with Optimality Explorer for AI-Driven Optimization of Electronic Systems
- Cadence Accelerates System Innovation with Breakthrough Integrity 3D-IC Platform
- Cadence Unveils Next-Generation Sigrity X for Up to 10X Faster System Analysis
- Arm, Cadence and Xilinx Introduce First Arm Neoverse System Development Platform for Next-Generation Cloud-to-Edge Infrastructure, Implemented on TSMC 7nm Process Technology
- GlobalFoundries and STMicroelectronics Finalize Agreement for New 300mm Semiconductor Manufacturing Facility in France
- Microchip Slashes Time to Innovation with Industry's Most Power-Efficient Mid-Range FPGA Industrial Edge Stack, More Core Library IP and Conversion Tools
- Consortium's Move Will Boost RISC-V Ecosystem, Thankfully
- Are Chiplets Enough to Save Moore's Law?
- Andes Technology Showcases Pioneering RISC-V CPU IP Solutions at RISC-V Summit Europe
- Nanusens announces that it can now create ASICs with embedded sensors
- Intel Foundry Services Ushers in a New Era
- Chiplet Pioneer Eliyan Achieves First Silicon in Record Time with Implementation in TSMC 5nm Process, Confirms Most Efficient Chiplet Interconnect Solution in the Multi-Die Era
- MediaTek Partners With NVIDIA to Provide Full-Scale Product Roadmap to the Automotive Industry
- Semidynamics announces largest, fully customisable Vector Unit in the RISC-V market, delivering up to 2048b of computation per cycle for unprecedented data handling
|E-mail This Article||Printer-Friendly Page|