Imperas simulation technology and RISC-V reference models updated to cover the RISC-V P Extension for SoC architecture exploration and early software development
Oxford, United Kingdom, July 12th, 2021 — Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced that Andes Technology Corp., a leading supplier of performance-efficient and extensible 32/64-bit RISC-V CPU cores and a Founding Premier member of the RISC-V International Association, has certified the Imperas reference models for the complete range of Andes IP cores with the new RISC-V P extension. Developers can now use the Imperas reference models to evaluate multicore design configuration options for SoC architecture exploration.
The open standard RISC-V ISA (Instruction Set Architecture) has a modular structure based on multiple independent extensions that offer dedicated and enhanced functionality to optimize a processor for the target application. The new SIMD/DSP extension, designated as ‘P’ in the specification description, supports efficient data processing applications and real-time requirements. The RISC-V International P Extension Task Group is in the final stages of submitting the specification to the official ratification process, which is expected to be completed within H2 2021.
The Imperas simulation technology enables fast and accurate virtual platforms that are central to modern SoC design and embedded software development. Working with lead customers, the Imperas models of the Andes cores have already been used for commercial projects, which are now implemented in silicon.
Optimizing a multicore design is one of the most challenging design tasks. Multiple independent processing units interacting with each other plus shared peripherals together with real-time processing tasks supporting a mix of OS/RTOS running firmware and application software. SoC architecture exploration allows a full evaluation of software running before the final decision and configuration of the hardware options. These virtual prototypes also support early software development, often many months before silicon prototypes are available. For final software testing, a virtual platform allows the actual binary code to be verified with access and visibility not available in real hardware or without compromising the software under test with additional test code.
“RISC-V is more than an ISA specification, it is a framework of flexibility; the real value is in the extensions and options available for processor core implementations,” said Dr. Charlie Su, President and CTO at Andes Technology Corp. “The RISC-V P extension within the Andes cores addresses the key real-time requirements in SIMD/DSP computations for new markets in audio/speech, IoT, tinyML and edge devices. Together with the Andes certified Imperas reference models, SoC developers can explore the next generation domain-specific solutions.”
“Embedded development depends on the optimized balance between hardware resources and software applications,” said Simon Davidmann, CEO at Imperas Software Ltd. “With the Imperas golden reference models, developers can explore full software development for all the Andes cores, including the new RISC-V P extension and Andes ACE custom instructions.”
About Andes Technology
Sixteen years in business and a Founding Premier member of RISC-V International, Andes is a leading supplier of high-performance/low-power 32/64-bit embedded processor IP solutions, and a main force to take RISC-V mainstream. Andes’ fifth-generation AndeStar™ architecture adopted the RISC-V as the base. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit cores with DSP, FPU, Vector, Linux, superscalar, and/or multicore capabilities. The annual volume of Andes-Embedded SoCs has exceeded 2 billion since 2020, and the cumulative volume has reached 7 billion.
For more information, please visit https://www.andestech.com.
Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, along with Open Virtual Platforms (OVP), promotes open-source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multicore systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.
For more information about Imperas, please see www.imperas.com.