MIPI D-PHY Tx-Only 2 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
Axiomise Unveils Intelligent Debug Solution for Formal Verification of RISC-V Cores
Identified 30 new bugs in WARP-V Family when Paired with Axiomise Formal App
LONDON –– January 3, 2022 –– Axiomise, the leading provider of cutting-edge formal verification consulting, training, services, and IP, today launched the industry’s first intelligent debug solution for formal verification of RISC-V cores.
Intelligent Rapid Analysis Debug and Reporting (i-RADAR) is available as a plugin in the Axiomise formalISA app that provides a complete end-to-end vendor-neutral formal verification solution for architectural validation of RISC-V cores. i-RADAR and formalISA were used to formally prove three new RISC-V cores from the WARP-V family.
“The formalISA app combined with i-RADAR found new bugs not previously found by other verification solutions,” remarks Dr. Ashish Darbari, CEO and founder of Axiomise and one of the foremost authorities in practical applied formal verification.
Axiomise also created a new formal verification solution for security verification of RISC-V cores and used it to identify several security vulnerabilities in multiple RISC-V cores. A paper describing the solution titled, “Comprehensive Processor Security Verification: A CIA problem,” will be presented in Design Automation Conference’s virtual format the week following in-person DAC.
|
Related News
- Axiomise Announces the Release of the Next-Generation RISC-V App
- Breker Verification Systems Unveils Easy-To-Adopt Integrity FASTApps Targeting RISC-V Processor Core, SoC Verification Scenarios
- Andes Technology Unveils the D45-SE RISC-V Processor Targeting ASIL-D Certification
- Codasip unveils versatile automotive-grade embedded RISC-V core
- Axiomise launches Essential Introduction to Practical Formal Verification Training
Breaking News
- Achronix and BigCat Wireless Collaborate to Deliver Unprecedented Power Efficiency and Performance for 5G/6G Wireless Applications
- Renesas Unveils Industry's First Automotive Multi-Domain SoC Built with 3-nm Process Technology
- LG and Tenstorrent Expand Partnership to Enhance AI Chip Capabilities
- CHERI Alliance Officially Launches, Adds Major Partners including Google, to Tackle Cybersecurity Threats at the Hardware Level
- Silicon Creations Celebrates Milestone with Delivery of 1,000th Production License for Fractional-N PLL
Most Popular
- Flex Logix Acquired By Analog Devices
- Arteris and MIPS Partner on High-Performance RISC-V SoCs for Automotive, Datacenter and Edge AI
- NanoXplore acquires Dolphin Design's ASIC business and strengthens its strategic position in aerospace
- SEMIFIVE Collaborates with Synopsys to Develop Advanced Chiplet Platform for High-Performance Multi-Die Designs
- Imagination DXS GPU officially certified as ASIL-B compliant
E-mail This Article | Printer-Friendly Page |