PCI-SIG Releases PCIe 6.0 Specification Delivering Record Performance to Power Big Data Applications
PCIe 6.0 specification reaches 64 GT/s transfer speeds, doubling the PCIe 5.0 specification data rate
January 11, 2022 -- BEAVERTON, Ore. -- PCI-SIG®, the organization responsible for the widely adopted PCI Express® (PCIe®) standard, today announced the official release of the PCIe 6.0 specification, reaching 64 GT/s.
Ad |
PCIe 6.0 Controller supporting Root Port, Endpoint, Dual-mode, Switch Port Configurations with native user interface ![]() Synopsys PCI Express 6.0 PHY IP on N5 ![]() |
PCIe 6.0 Specification Features
- 64 GT/s raw data rate and up to 256 GB/s via x16 configuration
- Pulse Amplitude Modulation with 4 levels (PAM4) signaling and leverages existing PAM4 already available in the industry
- Lightweight Forward Error Correct (FEC) and Cyclic Redundancy Check (CRC) mitigate the bit error rate increase associated with PAM4 signaling
- Flit (flow control unit) based encoding supports PAM4 modulation and enables more than double the bandwidth gain
- Updated Packet layout used in Flit Mode to provide additional functionality and simplify processing
- Maintains backwards compatibility with all previous generations of PCIe technology
PCI Express technology has served as the de facto interconnect of choice for nearly two decades. The PCIe 6.0 specification doubles the bandwidth and power efficiency of the PCIe 5.0 specification (32 GT/s), while providing low latency and reduced bandwidth overhead.
“PCI-SIG is pleased to announce the release of the PCIe 6.0 specification less than three years after the PCIe 5.0 specification,” said Al Yanes, PCI-SIG Chairperson and President. “PCIe 6.0 technology is the cost-effective and scalable interconnect solution that will continue to impact data-intensive markets like data center, artificial intelligence/machine learning, HPC, automotive, IoT, and military/aerospace, while also protecting industry investments by maintaining backwards compatibility with all previous generations of PCIe technology.”
“With the PCI Express SSD market forecasted to grow at a CAGR of 40% to over 800 exabytes by 2025, PCI-SIG continues to meet the future needs of storage applications,” said Greg Wong, Founder and Principal Analyst, Forward Insights. “With the storage industry transitioning to PCIe 4.0 technology and on the cusp of introducing PCIe 5.0 technology, companies will begin adopting PCIe 6.0 technology in their roadmaps to future-proof their products and take advantage of the high bandwidth and low latency that PCI Express technology offers.”
“There is a growing demand for ever-increasing performance in many segments in the data center such as high-performance computing and AI,” said Ashish Nadkarni, Group Vice President, Infrastructure Systems, Platforms and Technologies Group, IDC. “Within three to five years the application landscape will look very different and companies will likely begin updating their roadmaps accordingly. The advancement of an established standard like PCIe 6.0 architecture will serve the industry well in establishing composable infrastructure for performance intensive computing use cases.”
To learn more about PCI-SIG, visit www.pcisig.com. PCI-SIG members can download the full specification here.
PCIe 6.0 Specification: Evolving Performance for Data Centric Applications
Additional Resources
About PCI-SIG
PCI-SIG is the consortium that owns and manages PCI specifications as open industry standards. The organization defines industry standard I/O (input/output) specifications consistent with the needs of its members. Currently, PCI-SIG is comprised of over 800 industry-leading member companies. To join PCI-SIG, and for a list of the Board of Directors, visit www.pcisig.com.
|
Related News
- PCI-SIG® Announces PCI Express® 7.0 Specification to Reach 128 GT/s
- PCI-SIG Announces Upcoming PCI Express 6.0 Specification to Reach 64 GT/s
- PCI-SIG Releases PCI Express M.2 Specification Revision 1.0
- PCI-SIG Releases PCI Express 3.0 Specification
- PCI-SIG Releases PCI Express 2.0 Specification to Members for Review and Continues Innovation on the PCI Express Technology
Breaking News
- ShortLink AB joins X-FAB's Design & Supply Chain Partner Network and IP Portal
- HARMAN and proteanTecs Collaborate to Advance Predictive and Preventive Maintenance for Automotive Electronics
- Worldwide Silicon Wafer Shipments and Revenue Set New Records in 2022, SEMI Reports
- AI-designed Chips Reach Scale with First 100 Commercial Tape-outs Using Synopsys Technology
- Arm Q3 FY22 financial results
Most Popular
- U.S. Ban on Huawei Seen Widening China Chip War
- Denying China IC Manufacturing Tools
- Gartner Says Top 10 Semiconductor Buyers Decreased Chip Spending by 7.6% in 2022
- Arm Q3 FY22 financial results
- ZeroPoint Technologies raises EUR 3.2 million in seed funding to reduce energy consumption of data centers by more than 25%
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |