Proven Verification Leaders Collaborate on Open SoC Scenario Validation Standards, Methodologies and Metrics
SAN FRANCISCO –– July 11, 2022 –– Breker Verification Systems, the leading provider of advanced test content synthesis solutions, including RISC-V Cache Coherency, and Codasip, the leading supplier of customizable RISC-V processor IP, today announced an extensive technical collaboration to develop and improve rigorous verification processes for common RISC-V SoC scenarios.
Today’s announcement comes as Breker and Codasip demonstrate their RISC-V SoC verification and processor IP solutions at Design Automation Conference (DAC) in Booth #2528 and #1451, respectively, at Moscone West here.
As RISC-V processor developments extend more into the application processor space, the requirement for high-quality verification techniques that address common SoC scenarios such as cache coherency, security and power management has become critical. Typically, these processes consist of applying a range of algorithms to drive interleaved test content, a largely ad hoc process. Codasip’s and Breker’s core competencies in verification can be applied to the industry problem at large to establish a prescribed verification flow for SoC verification to increase the state of the art for the good of the entire RISC-V community.
“As the complexity of RISC-V processors for state-of-the-art systems continues to increase, testing the final SoC to ensure perfect operation in all conditions is both complex and essential,” remarks David Kelf, CEO of Breker Verification Systems. “Codasip’s expertise in this area coupled with Breker’s renowned solutions can be combined to provide a framework for SoC scenarios, such as cache coherency testing, that will bring precision and rigor to this increasingly complex challenge.”
“Codasip is building the highest quality RISC-V processors on the market, and an essential element of this to ensure exacting levels of operation in SoCs that make use of these devices,” notes Melaine Facon, Director Codasip Design Centre (France). “We are investing heavily in verification excellence and are delighted to work with Breker for the good of the entire RISC-V community and industry at large.”
Visit Breker and Codasip at DAC
RISC-V SoC verification and processor IP solutions demonstrations in the Breker and Codasip will be available today through Wednesday, July 13, from 10 a.m. until 6 p.m.
Send email to firstname.lastname@example.org or email@example.com to arrange a meeting or demonstration.
Codasip delivers leading-edge RISC-V processor IP and high-level processor design tools, providing IC designers with all the advantages of the RISC-V open ISA, along with the unique ability to customize the processor IP. As a founding member of RISC-V International and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded and application processors. Formed in 2014 and headquartered in Munich, Germany, Codasip currently has R&D centers in Europe and sales representatives worldwide. For more information about our products and services, visit www.codasip.com. For more information about RISC-V, visit www.riscv.org.
About Breker Verification Systems
Breker Verification Systems is a leading provider of Portable Stimulus solutions, a standard means to specify verification intent and behaviors reusable across target platforms. It is the first company to introduce graph-based verification and the synthesis of powerful test sets from intent-based, abstract scenario models based on AI planning algorithms. Breker’s Test Suite Synthesis and TrekApp library allows the automated generation of high-coverage, powerful test cases for deployment into a variety of UVM, SoC and Post-Silicon verification environments. Case studies that feature Altera (now Intel), Analog Devices, Broadcom, IBM, Huawei and other companies leveraging Breker’s solutions are available on the Breker website. Breker is privately held and works with leading semiconductor companies worldwide.