Neuromorphic Device with Low Power Consumption
By Maurizio Di Paolo Emilio, EETimes (August 1, 2022)
Compact, low–latency, and low–power computer systems are required for real–world sensory–processing applications. Hybrid memristive CMOS neuromorphic architectures, with their in–memory event–driven computing capabilities, present an appropriate hardware substrate for such tasks.
To demonstrate the full potential of such systems and drawing inspiration from the barn owl’s neuroanatomy, CEA–Leti has developed an event–driven, object–localization system that couples state–of–the–art piezoelectric, ultrasound transducer sensors with a neuromorphic computational map based on resistive random–access memory (RRAM).
CEA–Leti built and tested this object tracking system with the help of researchers from CEA–List, the University of Zurich, the University of Tours, and the University of Udine.
The researchers conducted measurements findings from a system built out of RRAM–based coincidence detectors, delay–line circuits, and a fully customized ultrasonic sensor. This experimental data has been used to calibrate the system–level models. These simulations have then been used to determine the object localization model’s angular resolution and energy efficiency. Presented in a paper published recently in Nature Communications, the research team describes the development of an auditory–processing system that increases energy efficiency by up to five orders of magnitude compared with conventional localization systems based on microcontrollers.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related News
- Tokyo Electron Device Announces New TB-OP-FCRAM Evaluation Board Released for Low Power Consumption Memory FCRAM
- MIPI RFFE (RF Front-End Control Interface) v3.0 Master and Slave Controller IP Cores for ultimate control of your RF Front-end Cellular or Base station SoC's with Low Power Consumption and Reduced Latencies
- Spectral Design & Test Inc. Announces 3rd Generation 45RFSOI Low Power SRAM Targeted at the 5G Mobile Device SoC Market
- Gowin Semiconductor Takes Leadership Position in Always-on Low Power FPGAs with GW1NZ-ZV Device Production
- Gidel Launches Lossless Compression IP that Reduces Storage Needs by Over 50%, Utilizing Only 1% of the FPGA, with Low Power Consumption
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation