Oct. 11, 2022 –
October 11, 2022. Bytom, Poland -- The DEMSCC - Dual channel Multiprotocol Enhanced Serial Communication Controller, means a brave new world for well-known serial IP users. The new IP Core is available with AXI, AHB, APB wrappers enabling ultimate functionalities for all modern microcontrollers, both from DCD-SEMI and other vendors.
Many controllers limit design functionality, because they’re very demanding with interrupts and with the time needed to service them to keep the data pipe full (it only has a 4 byte receive buffer). When the MCU is performing numerous other tasks and you want to scale up to higher data rates, then the MCU gets bogged down. – It’s a very common issue with this module – says Jacek Hanke, DCD-SEMI CEO - that is why we have developed and enhanced the DMESCC with higher TX and RX Buffers. In this solution buffers sizes are configurable, so you can select 64, 128, 256 or even more FIFO locations.
What is also important - all the other functionalities of the DMESCC, operate the same way as in the original Zilog implementation, this means that customers can change the old, inefficient design to a new more efficient and higher performance design and get the best long-term solution.
This multiprotocol combo with HDLC, UART, SPI, with bigger FIFO has been designed to make engineers’ life easier. – Our customers can configure the DEMSCC to handle all asynchronous formats regardless of data size, number of stop bits, or parity requirements – explains Jacek Hanke, DCD-SEMI CEO.
Control is done through the number of control and status registers for each channel separately. Within each operating mode, the DEMSCC also allows for protocol variations by checking odd or even parity bits, character insertion or deletion, CRC generation, checking break and abort generation and detection, and many other protocol-dependent features.
The ultimate functionality of the DEMSCC denotes its usability:
The DEMSCC provides two independent full-duplex channels, programmable for use in any standard asynchronous or synchronous data communication protocol. In Asynchronous mode transmission and reception can be accomplished independently on each channel with 5 to 8 bits per character, plus optional even or odd parity. The transmitters can supply one, one-and-half, or two stop bits per character and can provide a break output at any time. The receiver break-detection logic interrupts the CPU.
Additional information: https://www.dcd-semi.com/product/demscc/