RISC-V Summit brings together the global RISC-V community after a banner year
San Jose, Calif. – Dec. 13, 2022 – RISC-V International, the global open standards organization, highlighted the community’s impressive growth milestones and technical progress at the global RISC-V Summit, taking place Dec. 13-15 in San Jose, Calif. and virtually. RISC-V International has seen more than 26% membership growth year-over-year, with over 3,180 members across 70 countries. Today, there are more than 10 billion RISC-V cores in the market, and tens of thousands of engineers working on RISC-V initiatives globally.
“Our vision for 2022 was to bring RISC-V everywhere, and that has really come to fruition with RISC-V adoption and development in everything from automotive to aerospace to the data center, as well as consumer devices,” said Calista Redmond, CEO of RISC-V International. “There are already billions of RISC-V cores in the market with this groundswell, and we expect to see billions more in 2023 as companies and countries around the world embrace RISC-V.”
Some of the most important technical progress on RISC-V over the past year has been the community’s work on RISC-V Profiles to define versioned collections of instructions, behavior, and state that enable application portability between implementations. The public review for RISC-V Profiles RVI20, RVA20, and RVA22 just wrapped up and will be voted upon for ratification in Q1 of 2023.
The RISC-V community has also made strong progress on specifications and extensions, ratifying six this past year, with 10 additional specifications and extensions are expected to be ratified in the next 120 days.
The already ratified specifications include: wait on reservation, processor specific ABI (application Binary interface), efficient trace, supervisor binary interface (SBI), and standalone multiply. Wait on Reservation (Zawrs) is an ISA extension that allows power-conscious implementations to optimize power for certain memory operation. The process specific ABI (psABI) specifies the calling and linking conventions and tools to support them. Efficient trace (E-Trace) is a novel tracing standard designed specifically for RISC-V. The supervisor binary interface (SBI) defines the LINUX interface between the operating system and firmware. Standalone multiply (Zmmul) is an ISA extension that allows for using multiple without divide to support embedded solutions that do not want to spend the logic space on divide (known in general to be more costly).
The soon-to-be-ratified Crypto vector ISA extension also represents a key technical milestone. The Crypto vector extension will allow for the efficient implementation of cryptographic algorithms (like NIST). Implementing a loop for a common algorithm (AES128), for example, would take over 1000 RISC-V instructions to implement. Last year, RISC-V ratified Crypto scalar which brought the instruction count down to 75 and enabled great performance improvements; it is intended for places where logic space is at a premium, as it is fairly easy to implement. Crypto vector brings the number of instructions in many cases down to 1 and is intended for more rich implementations like edge servers or data center servers. Crypto vector enables implementers to realize a huge performance improvement.
Said Mark Himelstein, CTO of RISC-V International: “Thanks to thousands of contributors in the RISC-V community, we have made considerable progress on specifications. In addition to the six specifications already ratified this year, another 10 will be ratified in Q1 2023. A huge milestone this year was everyone’s work on RISC-V Profiles to enable compatible implementations and portability of RISC-V applications, helping to further fuel RISC-V adoption. Another standout is the Crypto vector ISA extension as it will provide huge performance gains for implementers.”
These technical achievements were made possible by the collaboration of RISC-V members across the 81 technical groups. More than 30 of those groups were added in 2022 alone to focus on fast-growth markets for RISC-V, such as security, system-on-chip infrastructure, automotive and AI/ML.
One of the most exciting developments this year has been the support of RISC-V from industry leaders across different markets. For example, NASA selected Microchip Technology to power the agency’s next High-Performance Spaceflight Computing (HPSC) processor, which will be used in future lunar and Mars surface missions; the new HPSC will use SiFive’s cores. Another huge milestone was Intel’s announcement of a $1 billion fund to build out its foundry ecosystem, with support from RISC-V members including Andes Technology, Esperanto Technologies, SiFive, and Ventana Micro Systems. There has also been strong support for RISC-V in Europe with the European Processor Initiative, India with the Digital India RISC-V (DIR-V) program, and China with a number of different initiatives, among state-sponsored programs in many other regions.
There have been significant updates to the RISC-V software ecosystem over the past year. Google’s Android Open Source Project (AOSP) started the upstream enablement of RISC-V. Bringing Android to RISC-V will help support a wide range of consumer-centric use cases ranging from mobile to in-car entertainment. Additionally, RISC-V International’s technical groups brought RISC-V support to many more software projects, covering all the stack. A glimpse of the progress includes coreboot, which provides open source firmware; OpenSSL, which offers a robust, commercial-grade toolkit for general-purpose cryptography and secure communication; and seL4, a high-assurance, high-performance operating system microkernel. Additionally, RISC-V support is in the works for: Alpine Linux, a security-oriented, lightweight Linux distribution which is key for containerized workloads; Network Security Services (NSS), a set of libraries designed to support cross-platform development of security-enabled client and server applications; Sparrow, a project to build a low-power secure embedded platform for Ambient ML applications. The list goes on as more communities and projects embrace RISC-V. Many other tools and projects have made updates to support RISC-V, including LibreOffice, Linux 6.0, LLVM/Clang 16, VLC media player, Renode, and Zephyr. Check out GitHub for information on RISC-V projects.
On the hardware side, RISC-V members have brought to market a wide variety of RISC-V solutions across verticals. Check out the RISC-V Exchange to see some of the latest solutions; more details on RISC-V announcements are also included further below. Additionally, RISC-V International expanded the RISC-V Developer Boards program to make development boards more accessible to the RISC-V community. To get a free RISC-V board or donate boards, please visit here.
RISC-V International has been working to build out its educational resources for the growing RISC-V community. Together with the Linux Foundation, RISC-V just rolled out a new online course, Foundations of RISC-V Assembly Programming (LFD117x), to help develop hardware-related RISC-V assembly programming knowledge and skills. Other available RISC-V courses include: Introduction to RISC-V (LFD110x), Building a RISC-V CPU Core (LFD111x), and RISC-V Toolchain and Compiler Optimization Techniques (LFD113x), each of which can be audited at no cost through the edX online learning platform.
Additionally, the first RISC-V Certification exam has launched to help those seeking entry-level RISC-V roles or to transition from another architecture. The RISC-V Foundational Associate (RVFA) certification exam, which is designed to test foundational knowledge of the RISC-V ISA, is available for immediate registration for $250; RISC-V Summit attendees can receive a 40% discount code through Dec. 19 with the code RVFA22.
These RISC-V courses and certification opportunities will continue to play a critical role as the RISC-V jobs market heats up. To learn more about RISC-V careers and opportunities, please visit here.
Members across the ecosystem have continued to innovate with cutting-edge RISC-V hardware and software solutions. Below are some highlights of recent member news:
- Andes Technology and Parasoft collaborated to provide seamless software testing tools for automotive functional safety applications.
- Andes Technology launched the AndesCore™ D23, a feature-rich, low-power, and highly-secured entry-level RISC-V Processor.
- Andes Technology unveiled its new RISC-V multicore 1024-bit vector processor: AX45MPV
- Ashling announced the availability of their new Vitra-XS Debug & Trace Probe.
- CAES won its first commercial U.S.-based license for its RISC-V/NOEL-V processor IP with Idaho Scientific, which specializes in solutions that prevent hardware and software security attacks.
- Codasip launched the SecuRISC5 initiative to provide its customers with safe and secure custom compute using highly verified reference designs combining Codasip IP and third-party technology.
- Codasip established Codasip Labs to accelerate the development and commercialization of advanced technologies including security, functional safety, and AI/ML.
- Codasip and Intel collaborated to provide universities with faster, simplified architectural exploration with Codasip RISC-V IP cores, the Codasip Studio development environment, and Intel’s FPGA platforms.
- Cortus announced two new RISC-V microcontrollers (MCUs) in the Lotus family for consumer devices and vehicles.
- Imperas and Andes made Imperas reference models available for the full range of Andes RISC-V processor IPs.
- Imperas and Imagination collaborated on providing virtual platform models for the Catapult RISC-V CPU family.
- Intel Pathfinder for RISC-V rolled out an array of new features, with support from more than 15 ecosystem partners.
- Microchip announced it is showcasing RISC-V-Based FPGA and space-compute solutions at RISC-V Summit.
- MIPS announced the availability of its first RISC-V IP core, the high performance and scalable eVocore P8700 multiprocessor.
- MIPS partnered with Mobileye to accelerate next generation autonomous driving technologies and advanced driver assistance systems with MIPS’ eVocore P8700 RISC-V multiprocessors.
- Solid Sands rolled out new enhancements to SuperGuard, which is a suite of professional tools for library qualification of safety-critical applications.
- Solid Sands highlighted that the company will be onsite at the RISC-V Summit to showcase its knowledge of how to qualify C and C++ standard libraries for safety-critical applications.
- XMOS unveiled a RISC-V compatible architecture for the fourth generation of its xcore platform.
Registration is still open for the RISC-V Summit, taking place Dec. 13-15 in San Jose, Calif. and virtually. To register, please visit: https://events.linuxfoundation.org/riscv-summit/register/. The full RISC-V Summit schedule is available here: https://events.linuxfoundation.org/riscv-summit/program/schedule/.
About RISC-V International
RISC-V International is the non-profit home of the open standard RISC-V Instruction Set Architecture (ISA), related specifications, and stakeholder community. More than 3,180 RISC-V members across 70 countries contribute and collaborate to define RISC-V open specifications as well as convene and govern related technical, industry, domain, and special interest groups. RISC-V combines a modular technical approach with an open, royalty-free license model — meaning that anyone, anywhere can benefit from the IP contributed and produced by RISC-V. RISC-V enables the community to share technical investment, contribute to the strategic future, create more rapidly, enjoy unprecedented design freedom, and substantially reduce the cost of innovation. To learn more, visit www.riscv.org.