English
Digital Blocks AMBA Peripherals I3C, I2C, eSPI, xSPI Controller IP Core Families Extend Leadership with enhancements containing feature-rich, system-level integration features.
GLEN ROCK, New Jersey, January 8, 2023 – Digital Blocks, a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA developers, announces updates to I3C, I2C, eSPI, xSPI Controller Verilog IP Core family offerings.
Digital Blocks Controller IP Core family members contain feature-rich, system-level integration features. Summary information is as follows:
| IP Core family | Brief Description of Configurations & Capabilities |
| I3C | I3C Master/Slave, I3C Master, & I3C Slave. Versions supporting I3C Basic specification available. I3C Slave versions either autonomous for register interface or AMBA interface to ARM or RISC-V processor. |
| I2C | Similar configurations as with I3C above. Advanced I2C capabilities include Hs-Mode, SCLK clock only (for low power), bridging to AMBA Master bus, and SMBUS. |
| xSPI | Similar configurations as with I3C & I2C above. |
| eSPI | Conforms to the eSPI specification |
Price and Availability
The Digital Blocks I3C, I2C, eSPI, xSPI Controller IP Core family members are available in synthesizable Verilog, along with a comprehensive simulation test suite, datasheet, and user manual. Full press release here: DB-I3C-I2C-eSPI-xSPI-Controller-Announcement.pdf For further information, product evaluation, or pricing, please go to Digital Blocks at www.digitalblocks.com
About Digital Blocks
Digital Blocks is a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA developers requiring best-in-class IP for AMBA Peripherals (DMA/I3C/I2C/SPI/eSPI Controllers), TFT LCD/OLED Display Controllers & Processors, 2D Graphics Hardware Accelerator Engines, Video Signal & Image Processing, and Low-Latency UDP/RTP Hardware Protocol Stacks.
Digital Blocks designs silicon-proven IP cores for technology systems companies, reducing customer’s development costs and significantly improving their time-to-volume goals. Digital Blocks is located at 587 Rock Rd, Glen Rock, NJ 07452 (USA).
|
||||||
Digital Blocks Hot IP
Related News
- Digital Blocks I2C & SPI Controller IP Core Families Extend Leadership in Sensor Interface to Host Processors with System-Level Features & Low Power
- Digital Blocks I2C & SPI Controller IP Core Families Extend Lead in Sensor Interface to Host Processors with System-Level Features & Low Power
- Digital Blocks Extends its I2C Controller IP Core Family with More Enhanced Capabilities & System-Level Features
- Digital Blocks Extends its I2C Controller IP Core Family with Enhanced Capabilities & System-Level Features
- Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with releases for core DMA Engines in RISC-V® & ARM® Systems and Peripherals to Memory Applications
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
|
E-mail This Article | 
|
|
Printer-Friendly Page |