Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
Bluespec collaborates with Synopsys to address growing verification demands for RISC-V design community
Industry-leading Synopsys VCS simulation and Verdi hardware/software debug solutions accelerate verification and validation of RISC-V cores
FRAMINGHAM, MASS. -- JANUARY 12, 2023 -- Bluespec Inc., announced today a collaboration with Synopsys to provide Synopsys reference methodologies for verification and hardware/software debug of RISC-V system designs with Bluespec RISC-V cores. As the open and extensible RISC-V Instruction Set Architecture (ISA) continues to see growing adoption, the demands for functional verification of RISC-V-based SoCs is also increasing. This collaboration provides the RISC-V community with proven flows that can be used to accelerate the verification and software/hardware debug of RISC-V processors and systems.
The first phase of the collaboration supplies reference methodology and scripts for Synopsys VCS® functional verification solution and the Synopsys Verdi® Debug System with Bluespec. These reference methodologies are Universal Verification Methodology (UVM) compliant, allowing mutual customers to seamlessly integrate into their verification flows. In addition, Synopsys and Bluespec are working on additional reference methodologies for static, formal, portable stimulus and FPGA synthesis.
“Creating custom implementations of a RISC-V-based ISA requires significant focus on achieving the highest verification coverage possible,” Kiran Vittal, senior director of Partner Alliances in the EDA Group at Synopsys. “Collaborating with key ecosystem companies, such as Bluespec, offers customers the ability to jumpstart their RISC-V designs with Synopsys’ optimized EDA flows and methodologies that will help increase verification productivity, performance and throughput.”
"RISC-V is providing an unprecedented number of CPU options, from suppliers to microarchitectures to custom instructions and more," said Charlie Hauck, CEO of Bluespec Inc. "We are happy to be collaborating with the EDA leader Synopsys to provide straightforward design, verification and validation flows to safely and efficiently navigate the RISC-V landscape."
Bluespec offers a broad range of RISC-V-based soft processor IP, a complete RISC-V software development environment running hardware-accurate RISC-V cores in an FPGA-enabled cloud and a turnkey hardware acceleration tool for developing innovative high-performance, low-power RISC-V subsystems. Bluespec provides three classes of RISC-V processors: the ultra-low resource count microcontroller family (MCU), the bare metal/RTOS family (BMR), which is optimized for performance and resource utilization, and a Single Core Linux (SCL) family for applications that run on top of Linux. As part of the collaboration with Synopsys, Bluespec will include reference scripts with the delivery of its processor IP to customers.
The Synopsys Verification Family of products are built from the industry's fastest engines, including Virtualizer™️ virtual prototyping, VC SpyGlass®️ static and VC Formal®️ verification technologies, VCS simulation, ZeBu®️ emulation, HAPS®️ prototyping, Verdi debug and VC Verification IP (VIP). Newly enhanced native integrations enable performance gains between all verification engines, accelerating time to market for complex RISC-V-based SoC designs.
The reference methodologies are available from Bluespec. Please contact sales@bluespec.com for more information.
About Bluespec
Bluespec provides RISC-V tools and silicon IP that enable companies to exploit the freedom to innovate and cost reduction that RISC-V enables. We provide a complete RISC-V software development environment running on fast, hardware-accurate RISC-V cores in an FPGA-enabled cloud, and a turnkey hardware acceleration tool for developing innovative high-performance low-power RISC-V subsystems. For more information on Bluespec, Inc. visit http://www.bluespec.com.
|
Related News
- Imperas Collaborates with Synopsys on SystemVerilog based RISC-V Verification
- Imperas Expands Partnership with Valtrix to Address Growing RISC-V Verification Market
- Imperas Collaborates with Mentor on RISC-V Core RTL Coverage Driven Design Verification Analysis
- SiFive Selects Synopsys Verification Continuum Platform for Advanced RISC-V Processor Designs
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |