Analog IPs Automate Integration, Tune to Fab Nodes
By Majeed Ahmad, EETimes (January 12, 2023)
System-on-chip (SoC) designs with heterogeneous voltage domains are increasingly moving away from custom analog IP to automated implementation so design engineers don’t have to worry about schedule slips caused by manual analog customizations. It also saves chip designers several months in the design process, while making analog circuits less susceptible to on-chip surroundings.
It’s important to note that automatically generated analog IP isn’t synonymous with off-the-shelf analog IP. Rather, analog IP generators bring the previously generated custom-design blocks into the design flow and employ specialized tools to tailor a suitable IP within hours. That, in turn, saves a lot of integration time and effort.
One of the key challenges that semiconductor engineers face when analyzing their solutions, however, revolves around how much analog designs can shrink when moving from one chip manufacturing process node to another. In other words, there are certain analog building blocks that don’t scale adequately to smaller IC manufacturing nodes. Moreover, while digital logic is getting cheaper in modern SoCs, not all analog functions can be incorporated economically.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related News
- Using Agile Analog's process-agnostic Analog IPs can help solve current Semiconductor capacity challenges
- USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP in 12nm, 16nm and 22nm process nodes with simple integration and flexible customization is ready for immediate licencing for your advanced SoC design
- Analog Bits to Present Papers, Demo of N5 Working Silicon, and Roadmap on IPs for TSMC N4 and N3 Processes
- Defacto enables ETRI to Automate IP Integration and Build Complex AI Chips
- Is analog IC fab renaissance in the works?
Breaking News
- IAR Systems fully supports the brand-new Industrial-Grade PX5 RTOS
- Axiomise Accelerates Formal Verification Adoption Across the Industry
- Fluent.ai Offers Embedded Voice Recognition for Cadence Tensilica HiFi 5 DSP-Based True Wireless Stereo Products
- intoPIX to feature TicoXS FIP technology for premium 4K & 8K AVoIP wireless AV at ISE 2023
- Sevya joins TSMC Design Center Alliance
Most Popular
- Weebit Nano nears productisation, negotiating initial customer agreements
- Cadence Quantus FS Solution, a 3D Field Solver, Achieves Certification for Samsung Foundry's SF4, SF3E and SF3 Process Technologies
- Sevya joins TSMC Design Center Alliance
- Avery Design Systems and CoMira Announce Partnership To Enable UCIe-Compliant Chiplet Design
- Open Compute Project Foundation and JEDEC Announce a New Collaboration