NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)
Tiempo Secure's new TESIC RISC-V IP successfully passes SERMA CC EAL5+ security assessment tests
Grenoble, France – July 3, 2023 – Tiempo Secure’s latest TESIC design, a Secure Element targeting applications such as iSIM, eSE, Payment, UWB, Digital ID, IoT security and Mobile Application Processors, has successfully passed SERMA CC EAL5+ AVA VAN.5 security testing, further demonstrating Tiempo’s unique security expertise. Tiempo Secure, leveraged its long-standing know-how in the field of security IP for microelectronics, to deploy its TESIC design with a RISC-V core. This new IP is critical for any Secure Element or Secure Enclave – an essential technology for building a certified secure component, to guarantee security for IoT wired or wireless communications, iSIM, root of trust secure designs, and HSM.
TESIC is Tiempo Secure’s security architecture, which now includes a RISC-V MCU, memories (ROM, RAM, Cache, Crypto-RAM, and MRAM non-volatile memory), random number generators, security sensors, and asynchronous crypto-accelerators, to support various types of symmetrical and asymmetrical cryptographic algorithms. Based on this IP, Tiempo Secure has designed a RISC-V test chip that was successfully evaluated by SERMA. To conduct the security evaluation, the Tiempo Secure design was manufactured in the form of a test chip, using Global Foundry GF22 FDX technology with MRAM. This also enabled Tiempo to validate the compatibility of TESIC with GF22 technology.
During the series of tests which were carried out over 5 months, particular emphasis was placed on side channel attacks and fault attacks. To reach the highest security assessment level, the die was packaged without resin, therefore making it more vulnerable and boosting the potential success rates of attacks. The result of the evaluation was successful, enabling Tiempo to validate both the hardware and software countermeasures implemented in the circuit that had been subjected to the tests.
Marc Renaudin, Tiempo Secure co-founder, and Chief Technology Officer commented “We are very satisfied with the outcome of the evaluation that was carried out by SERMA. This proves that our design will be ready for certification, and it also enables us to learn and continuously improve our processes and security expertise, thanks to the insights we gain from this type of independent lab evaluation”.
About SERMA:
SERMA Safety & Security, a unit of SERMA Group, is an assessment lab evaluating complex security products, ranging from microchips to complete hardware/software systems. It has numerous accreditations (ANSSI, EMVCo, GlobalPlatform, PCI, NIST, …) and is ITSEF approved by the ANSSI.
About Tiempo Secure:
Tiempo Secure is a leading French DeepTech company, specializing in the design of IP solutions and key secure elements, for strategic embedded security systems (IoT, Mobile, Automotive, Medical, Payment, Defense, Smart Grid…). Located near Grenoble and the French Alps, Tiempo is part of the high-tech ecosystem at the heart of Inovallée. Its user-driven innovation mindset and strong international customer base are key to its success. Backed by private investment companies, the company is growing fast in a dynamic cybersecurity market to secure the ever-increasing number of connected devices. Tiempo Secure offers a wide range of off-the-shelf Secure Elements (TESIC range) for integration into “System-on-Chip” (SoC) components, enabling maximum security levels (Common Criteria EAL5+ certified) for connected components.
For more information: www.tiempo-secure.com
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