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Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
DVB-C2 LDPC/ BCH Decoder FEC IP Core From Global IP Core
October 25, 2023 - Global IP Core Sales - In Digital video broadcasting for cable systems systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes concatenated with BCH (Bose Chaudhuri Hocquenghem) codes, allowing Quasi Error Free operation close to the Shannon limit.
Features include:
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DVB-C2 LDPC/ BCH Decoder IP Core  |
- Irregular Parity Check Matrix
- Layered Decoding
- Minimum Sum Algorithm
- Configurable Number of Iterations
- Soft Decision Decoding
- ETSI EN 301 769 V1.3.1 (2015-10) compliant
IP Deliverables:
- Synthesizable Verilog
- System Model (Matlab) and documentation
- Verilog Testbenches
- Documentation
- FPGA testing environment
Please contact us for a Product Brief (PB) at info@global-ipc.com or check out our product portfolio at www.global-ipc.com
About Global IP Core Sales
Global IP Core Sales® was founded in 2021 and provides state-of-the-art IP Cores for the Semiconductor market. The majority of our products are silicon proven and can be seamlessly implemented into FPGA and ASIC technologies. Global IP Core Sales® will assist you with your IP Core and integration needs. Our mission is to grow your bottom line.
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