55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
Tenstorrent Selects Blue Cheetah Chiplet Interconnect IP For Its AI and RISC-V Solutions
SUNNYVALE, Calif., Feb. 6, 2024 -- Tenstorrent and Blue Cheetah Analog Design today announced that Tenstorrent has licensed Blue Cheetah's die-to-die interconnect IP for its AI and RISC-V chiplet solutions. By selecting Blue Cheetah, Tenstorrent aims to accelerate its own as well as its customers' and partners' development of chiplet-based AI and RISC-V solutions.
"Blue Cheetah is unique in its ability to provide customizable standards-based die-to-die interconnect solutions that support the full range of capabilities and process technologies we, our partners, and our customers need." ~Jim Keller, CEO of Tenstorrent
Related |
Bunch of Wires [BoW] PHY |
"Blue Cheetah is unique in its ability to provide customizable standards-based die-to-die interconnect solutions that support the full range of capabilities and process technologies we, our partners, and our customers need," said Jim Keller, CEO of Tenstorrent. "Partnering with Blue Cheetah enables us to foster a chiplet-based ecosystem ready for both current and future system designs."
Blue Cheetah currently provides its chiplet interconnect IP solutions in 4 nm, 5nm, 7nm, 12nm, and 16nm process technologies. Its customizable die-to-die interconnect solutions enable customers to create leading products using chiplets optimized for a wide variety of end markets, achieving more cost-effective scaling and greater IP reuse.
"Tenstorrent delivers highly customized, high-performance AI and RISC-V chiplet solutions tailored to specific workloads and applications," said Elad Alon, CEO of Blue Cheetah. "Customizable die-to-die interfaces are an essential component of these solutions and enable developers to create cost-effective multi-chip designs that deliver powerful performance and next-level energy efficiency."
Blue Cheetah's BlueLynx D2D interconnect subsystem IP provides physical (PHY) and link layer chiplet interfaces and supports both Open Compute Project (OCP) Bunch of Wires (BoW) as well as Universal Chiplet Interconnect Express (UCIe). BlueLynx connects to on-die buses/Networks-on-Chip (NoCs) with a wide variety of standards, including AMBA® 4 CHI, AXI, ACE, and more.
About Blue Cheetah Analog Design
Blue Cheetah provides rapidly customizable standards-based die-to-die interconnect solutions for chiplets. Its state-of-the-art semiconductor IP solutions are process-adaptable and customizable to achieve industry-leading power, performance, and area for high-performance computing, AI/ML, networking, mobile, and many other applications. The company's BlueLynx platform provides chip makers the fastest, lowest-risk path to application-optimized chiplet interconnect solutions. Blue Cheetah was founded in 2018 and is headquartered in Sunnyvale, California. Visit https://www.bcanalog.com/.
About Tenstorrent
Tenstorrent is a next-generation computing company that builds computers for AI. Headquartered in the U.S. with offices in Austin, Texas, and Silicon Valley, and global offices in Toronto, Belgrade, Seoul, Tokyo, and Bangalore, Tenstorrent brings together experts in the field of computer architecture, ASIC and chiplet design, RISC-V CPU IP, and neural network compilers. Tenstorrent is backed by Fidelity, Hyundai Motor Group, Eclipse Ventures, Real Ventures, Archerman Capital, and Samsung Catalyst Fund among others.
For more information on Tenstorrent visit www.tenstorrent.com
|
Related News
- Tenstorrent RISC-V and Chiplet Technology Selected to Build the Future of AI in Japan
- YorChip, Inc. announces its first Chiplet for Edge AI applications with IP licensed from Semidynamics, the leader in RISC-V IP based in Barcelona
- Jim Keller on AI, RISC-V, Tenstorrent's Move to Edge IP
- Tenstorrent Partners with LG to Build AI and RISC-V Chiplets for Smart TVs of the Future
- Blue Cheetah Demonstrates Industry Leading Silicon-Proven Die-to-Die Interconnect Solution for Chiplets
Breaking News
- Thalia's AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%
- TSMC plans 1.6nm process for 2026
- Qualitas Semiconductor Partners with TUV Rheinland Korea to Enhance ISO 26262 Functional Safety Management System
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
Most Popular
- Controversial former Arm China CEO founds RISC-V chip startup
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
E-mail This Article | Printer-Friendly Page |