RaiderChip launches its Generative AI hardware accelerator for LLM models on low-cost FPGAs

The startup pioneers Edge Generative AI inference on small devices, thanks to the efficiency of its AI accelerator IP core: the GenAI v1

Spain, June 4th, 2024 -- The company, which recently announced its first Generative AI Hardware accelerator, goes one step further, offering a turn-key solution for LLM inference now available on a wide range of low-cost FPGA devices.

RaiderChip GenAI v1 running the Phi-2 LLM model on a Versal FPGA with a single Memory Controller

RaiderChip’s v1 design leverages 32-bits floating point arithmetic, which provides full precision, allowing direct usage of original LLM model weights, without any modification or quantization. This preserves the full intelligence and reasoning capabilities of the raw LLM models, as their creators intended them.

This full precision is coupled with real-time AI LLM inference speeds: “Our design’s efficiency edge allows customers to run unquantized LLM models at full interactive speed, on limited memory bandwidths where competitors are more than 20% slower, especially faster than CPU based inference solutions”, explains RaiderChip’s team.

The GenAI v1 IP core is already available for FPGAs of every sub-family in the AMD Versal FPGA line-up, as well as earlier UltraScale Series devices, and more: “Our IP cores are target-agnostic, and can also be implemented on different FPGA vendor devices, following customer’s requirements for logic resources and inference speed.” the team highlights.

A standout feature of RaiderChip’s solutions is the plug’n’play nature of its IP cores, using only the minimal number of industry standard AXI interfaces. With the provided IP blocks the GenAI v1 becomes a simple peripheral: fully controllable from the customer’s Software.

The introduction of FPGAs for Generative AI Acceleration expands the available options for local AI inference of LLM models. Furthermore, their reprogrammable nature makes them ideal in the context of explosive innovation in the AI field, where new models and algorithmic upgrades appear on a weekly basis, where FPGAs allow field updates of already deployed systems.

More information at https://raiderchip.ai/technology/hardware-ai-accelerators