Analog Bits to Demonstrate Power Management and Embedded Clocking and High Accuracy Sensor IP at the TSMC 2024 Open Innovation Platform Ecosystem Forum
Sunnyvale, CA, September 23, 2024 - Analog Bits (www.analogbits.com), the industry’s leading provider of low-power mixed-signal IP (Intellectual Property) solutions will be demonstrating their newest LDO IP, Power supply droop detectors, Embedded Clock LC PLL’s, and more in TSMC N3P process at their booth at the TSMC 2024 Open Innovation Platform Ecosystem Forum in Santa Clara Convention Center, Santa Clara, California. This demonstration is showcasing Analog Bits’ industry leading portfolio of Mixed Signal IP in advanced 3nm, 4nm, and 5nm processes. Analog Bits has also taped out their next generation N2P IPs.
“Analog Bits continues to innovate and solve harder SoC design challenges for customers designing in N3 and N2 processes which manifests as novel IP’s,” said Mahesh Tirupattur, Executive Vice President at Analog Bits. “With SoC’s increasingly multicore managing power into the cores is imperative. We have designed novel LDO macros that can be easily scaled, arrayed and shared adjacent to CPU cores and simultaneously monitoring power supply health with our detector macros allowing customers to balance power real time. It is like PLL’s that maintain clocking stability; we are now able to offer IP’s to maintain power integrity in real time. Come and see our demos and also come and sample Analog Bits 2024 holiday wine at our booth.”
- When: September 25th, 2024
- Location: Santa Clara Convention Center, Booth #708
- Register
Resources
To learn more about Analog Bits' foundational analog IP, visit www.analogbits.com or email us at info@analogbits.com.
About Analog Bits
Founded in 1995, Analog Bits, Inc. (www.analogbits.com), is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs.
Our products include precision clocking macros, Sensors, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s.
With billions of IP cores fabricated in customer silicon, from 0.35 micron to 3nm processes, Analog Bits has an outstanding heritage of "first-time-working” with foundries and IDMs.
|
Related News
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- Analog Bits to Demonstrate Automotive Grade IP's Including a Novel High Accuracy Sensor at TSMC 2023 North America Open Innovation Platform Ecosystem Forum
- Analog Bits to Demonstrate New High Performance and Ultra-Low Power SERDES IP at TSMC Open Innovation Platform Ecosystem Forum
- Analog Bits to Demonstrate Pinless PLL and Sensor IP in TSMC N4 and N5 Processes at TSMC 2022 North America Open Innovation Platform® Ecosystem Forum
- Analog Bits to demonstrate Low Power SERDES at TSMC's Open Innovation Platform Ecosystem Forum
Breaking News
- Movellus and RTX's SEAKR Engineering Collaborate on Advancing Mission-Critical ASICs
- Village Island Enhances its AI100 with intoPIX's JPEG XS Technology for Advanced Real-Time Analysis
- QuickLogic Announces $1.4 Million Incremental Funding Modification for its Strategic Radiation Hardened Program
- Silicon-Proven MIPI CSI-2 & DSI-2 Tx/Rx IP Cores for your Camera & Display SoCs
- Intel brings 3nm production to Europe in 2025
Most Popular
- Intel brings 3nm production to Europe in 2025
- Qualcomm initiates global anti-trust complaint about Arm
- VeriSilicon introduces AcuityPercept: an AI-powered automatic ISP tuning system
- RISC-V in Space Workshop 2025 in Gothenburg
- Avant Technology Partners with COSEDA Technologies to Enhance System-Level Software Solutions
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |