CHERI Protects Memory at the Hardware Level

Jamie Broome, chief product officer for automotive business and product management at Codasip, explained the role and importance of the CHERI Alliance and described Codasip’s new L730 processor focused on security and customization.

By Saumitra Jagdale, EETimes Europe (February 4, 2025)

Software-based security solutions have improved system protection but remain fundamentally vulnerable, often imposing performance tradeoffs due to their reliance on continuous monitoring and computational overhead. As cyberthreats become more sophisticated, attackers find new ways to exploit software-layer weaknesses. This has driven a shift toward hardware-based security, which offers more resilient protection by integrating security mechanisms directly into the foundational computing infrastructure.

Unlike software, hardware security tackles vulnerabilities at their root, creating a barrier that is both difficult to penetrate and effective in terms of performance. The Capability Hardware Enhanced RISC Instructions (CHERI) technology, developed by the University of Cambridge and adopted by a group of organizations and governments through the CHERI Alliance, follows this approach.

In an interview with EE Times Europe, Jamie Broome, chief product officer for automotive business and product management at Codasip, explained the role and importance of the CHERI Alliance and described Codasip’s new L730 processor focused on security and customization.

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