Mar. 17, 2025 –
By Karl Freund, Founder and Principle Analyst, Cambrian-AI Research
EETimes (March 14,2025)
Synopsys recently launched two new hardware-assisted verification (HAV) systems, intended to address the need for specialized hardware to manage the complexity of modern chip design. In this article, we look at the rationale for HAV and look into the two new systems.
The rationale for HAV hardware
In a recent interview, Frank Schirrmeister, executive director of strategic programs at Synopsys, provides some insights into large-scale chip and chiplet designs.
Designing AI accelerator chips is an exceptionally complex endeavor. Modern chips integrate billions of transistors and diverse processing units (CPUs, NPUs, GPUs, etc.), all working in parallel. Verifying such complexity with traditional simulation is daunting—it is not just for functional correctness but also for ensuring power efficiency and performance targets are met under real workloads.
New AI accelerators typically employ workload-specific optimizations (e.g. low-precision arithmetic, novel dataflows) that demand extensive architectural validation. The sheer scale of operations (often quadrillions of cycles for complete verification makes software simulation alone infeasible).