32-bit RISC-V embedded processor with TUV SUD ISO 26262 ASIL B certification
UltraSoC delivers industry's first RISC-V processor trace IP
January 25, 2018 -- UltraSoC, the leading developer of embedded analytics technology, today announced general availability of its RISC-V processor trace solution, an industry first and a key enabler within the RISC-V ecosystem. The addition of trace capabilities means that UltraSoC provides the most comprehensive RISC-V commercial debug solution.
Last June the company announced plans to develop processor trace, when it also detailed a trace specification to be considered for adoption as part of the RISC-V open standard.
UltraSoC’s solution is backed by major RISC-V processor vendors including Andes, Codasip, Microsemi, Roa Logic, SiFive and Syntacore, and tools vendors. As well as a stand-alone IP module for integration with UltraSoC’s SoC architecture, the company offers a variety of packaged options to get RISC-V designers up-and-running quickly without necessarily using UltraSoC for other functionality. These range from a lightweight package that combines simple run-control with USB as the debug interface; to more sophisticated solutions with both run control and trace, and interfacing via either JTAG or UltraSoC’s proprietary non-intrusive, bare-metal USB. UltraSoC remains the only company that supports all of the main run control options offered within the RISC-V ecosystem.
Rick O’Connor, executive director of the non-profit RISC-V Foundation, commented: “RISC-V is redefining the SoC value proposition: a key part of that is building a much more open and robust ecosystem than developers have been used to. On the technical level, full availability of processor trace is a key part of that development ecosystem. Within the RISC-V Foundation, we’re working to standardize the interfaces to RISC-V cores that provide processor trace; we’re delighted to see UltraSoC supporting that effort, while also delivering commercially.”
Processor trace functionality allows the behavior of a program to be viewed in detail, instruction-by-instruction, and is a key requirement for system developers. The UltraSoC RISC-V trace encoder supports both 32 and 64-bit RISC-V designs and the IP block integrates smoothly with the rest of the UltraSoC portfolio, supporting open and industry standard architectures to put self-analytic capabilities at the heart of SoCs. UltraSoC’s embedded analytics supports design teams, helping to manage complexity and improving time to market, design costs, reliability, safety and security in applications from automotive to enterprise IT and the IoT.
Since UltraSoC announced its RISC-V trace solution last year, the company’s involvement in the ecosystem for the open source architecture has progressed significantly with endorsements from more processor vendors and partners. In September, UltraSoC announced that its embedded analytics IP will be available through the SiFive DesignShare ecosystem that gives any company, inventor or maker the ability to harness the power of custom silicon. In November, UltraSoC announced it has been selected for use in Microsemi’s RISC-V product range.
UltraSoC will be at Embedded Word 2018 (Nürnburg, Germany, 27th February – 1 March), exhibiting within the RISC-V booth in hall 3A, booth 3A-419. UltraSoC CEO Rupert Baines has been selected to present a paper at 10am, on 27th February alongside Russ Klein of Mentor Graphics, entitled ‘RISC-V: Emulation and Rich, Non-Intrusive Analytics Address Verification Complexity’. The session will form part of the RISC-V Class, a full day of RISC-V focused discussions and presentations. For more details on the event and to arrange a meeting, visit the event page on the UltraSoC website.
|
Related News
- UltraSoC announces industry's first processor trace support for RISC-V
- Achronix FPGAs Add Support for Bluespec's Linux-capable RISC-V Soft Processors to Enable Scalable Processing
- StarFive's RISC-V based JH-7110 intelligent vision processing platform adopted VeriSilicon's Display Processor IP
- Nuclei System Technology collaborates with Siemens to deliver RISC-V Processor Trace Encoder solution
- Ventana Introduces Veyron V2 - World's Highest Performance Data Center-Class RISC-V Processor and Platform
Breaking News
- Alphawave Semi announced today a refocussing of the Board of Directors after reaching the three-year milestone since the Company's IPO
- Synopsys and Samsung Electronics Collaborate to Achieve First Production Tapeout of Flagship Mobile CPU with Leading Performance on Samsung Foundry's GAA Process
- Worldwide Silicon Wafer Shipments Dip 5% in Q1 2024, SEMI Reports
- GOWIN's progress in global automotive market gathers momentum with award of ISO 26262 certification for its FPGA design environment
- PCI-SIG® Announces CopprLink™ Cable Specifications for PCIe® 5.0 and 6.0 Technology
Most Popular
- Silvaco Announces Launch of Initial Public Offering
- TSMC's A16 Process Moves Goalposts in Tech-Leadership Game
- Radiation-Tolerant PolarFire® SoC FPGAs Offer Low Power, Zero Configuration Upsets, RISC-V Architecture for Space Applications
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- QuickLogic Releases Aurora 2.6 with Expanded Operating System Support and Up to 15% Faster Performance
E-mail This Article | Printer-Friendly Page |