JEDEC Publishes DDR4 NVDIMM-P Bus Protocol Standard
ARLINGTON, Va., USA – February 17, 2021 – JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD304-4.01 DDR4 NVDIMM-P Bus Protocol. The JEDEC NVDIMM-P standard will enable the industry to create advanced memory solutions that benefit from the enhanced system performance and novel data availability offered by Persistent Memory devices. JESD304-4.01 DDR4 NVDIMM-P is available for download from the JEDEC website.
As demand for DRAM capacity and bandwidth continues to grow, Hybrid DIMM technologies such as NVDIMM-P provide an innovative method for attaching emerging Persistent Memory in computing systems. Combining the access speeds of DDR with the reliability and capacity of non-volatile memories gives design engineers a new approach to data management. Much more than a standard DIMM specification, NVDIMM-P provides a full transactional interface protocol compatible with standard DRAM DIMMs along with a firmware programming model for the modules. NVDIMM-P simultaneously maximizes both re-use and flexibility by minimizing system host changes, providing an interface of the lowest latency to emerging memory, and offering flexible support for varied Persistent Memory media characteristics and use cases.
NVDIMM-P enables:
- Persistence: lowest latency and high bandwidth access to Persistent Memory modules in a system
- Abstraction of Memory Media: enabling most any memory media on the DDR channel
- Higher Memory Capacity: supports expanded memory addressing
- Plug and Play Interoperability: physically plugs into standard dual in-line memory module (DIMM) sockets and run-time interoperable with DDR DRAM DIMMs on the same bus
Key features include:
- Fully compatible with existing DDR channels (Physicals, Electricals, Protocol, Clocking)
- Minimal to no pin adder in CPU socket
- Protocol support of non-deterministic latency for data reads
- Transactional operations for ensuring data is preserved in Persistent Memory
- Latency support from NAND Flash down to DRAM latency (at module level)
- Self-contained reliability + link error protection
Mian Quddus, Chairman of the JEDEC Board of Directors, said: “Increasing performance requirements are driving the need for more advanced technologies, and the standardization of the new generation Persistent Memory modules such as NVDIMM-P will be essential to fulfilling those needs.” He added, “We invite all interested engineers worldwide to visit the JEDEC website for more information about JEDEC membership and participation in JEDEC standards-setting activities.”
About JEDEC
JEDEC is the global leader in the development of standards for the microelectronics industry. Thousands of volunteers representing over 300 member companies work together in more than 100 JEDEC technical committees and task groups to meet the needs of every segment of the industry, manufacturers and consumers alike. The publications and standards generated by JEDEC committees are accepted throughout the world. All JEDEC standards are available for download from the JEDEC website. For more information, visit www.jedec.org.
|
Related News
- JEDEC Publishes GDDR7 Graphics Memory Standard
- JEDEC Publishes New CAMM2 Memory Module Standard
- JEDEC Publishes New Standard to Support CXL Memory Module Implementation
- JEDEC Publishes Automotive Solid State Drive (SSD) Device Standard
- JEDEC Publishes HBM3 Update to High Bandwidth Memory (HBM) Standard
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- SEMIFIVE Starts Mass Production of its 14nm AI Inference SoC Platform based Product
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024
E-mail This Article | Printer-Friendly Page |