32-bit RISC-V embedded processor with TUV SUD ISO 26262 ASIL B certification
ARM pushes chiplets and 3D packaging for Neoverse chips
By Nick Flaherty, eeNews Europe (April 27, 2021)
ARM has launched an enhanced mesh interconnect IP for its high performance Neoverse processor cores that enables more use of chiplets and 3D packaging.
Chiplets allows separate chips to be used in the same package to provide high speed data links or stacked memory. The CMN-700 supports 144 end points for 128 cores plus chiplets and memories, rather than the limit of 64 for the previous CMN-600.
“CMN-700 [is] a key element for constructing high-performance Neoverse V1 and Neoverse N2-based SoCs,” said Chris Bergey, SVP and GM, Infrastructure Line of Business at ARM. “Platform IP is essential which is why we developed the CMN700 mesh interconnect with DDR5 support and multichip capabilities,” he said. “It adds CXL to build host or end point devices and the the other key multichip upgrade was for multi-die and chiplet integration and this will open new doors and allow more flexibility,” he said.
E-mail This Article | Printer-Friendly Page |
|
Arm Ltd Hot IP
Related News
- Google Cloud Delivers Customized Silicon Powered by Arm Neoverse for General-Purpose Compute and AI Inference Workloads
- Arm Updates CSS Designs for Hyperscalers' Custom Chips
- Faraday Collaborates in Arm Total Design to Provide Arm Neoverse CSS-based Design Services
- How the Worlds of Chiplets and Packaging Intertwine
- Faraday Unveils 2.5D/3D Advanced Package Service for Chiplets
Breaking News
- Alphawave Semi announced today a refocussing of the Board of Directors after reaching the three-year milestone since the Company's IPO
- Synopsys and Samsung Electronics Collaborate to Achieve First Production Tapeout of Flagship Mobile CPU with Leading Performance on Samsung Foundry's GAA Process
- Worldwide Silicon Wafer Shipments Dip 5% in Q1 2024, SEMI Reports
- GOWIN's progress in global automotive market gathers momentum with award of ISO 26262 certification for its FPGA design environment
- PCI-SIG® Announces CopprLink™ Cable Specifications for PCIe® 5.0 and 6.0 Technology
Most Popular
- Silvaco Announces Launch of Initial Public Offering
- TSMC's A16 Process Moves Goalposts in Tech-Leadership Game
- Radiation-Tolerant PolarFire® SoC FPGAs Offer Low Power, Zero Configuration Upsets, RISC-V Architecture for Space Applications
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- QuickLogic Releases Aurora 2.6 with Expanded Operating System Support and Up to 15% Faster Performance