Industry Articles
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A 55-nm Ultra Low Leakage SRAM Compiler with Optimized Power Gating Design
(Monday, March 14, 2011)
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Analog switches in D-PHY MIPI dual camera/dual display applications (Part 1 of 2)
(Monday, March 14, 2011)
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Hardware/Software integration: Closing the gap
(Monday, March 14, 2011)
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Planning reset strategy: Flow & functionality in OVC
(Thursday, March 10, 2011)
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How manycore will reshape EDA
(Wednesday, March 9, 2011)
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Major changes expected for physical verification tools as designs move into 28nm and below
(Tuesday, March 8, 2011)
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Using PCI Express as a fabric for interconnect clustering
(Tuesday, March 8, 2011)
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Hardware Co-Verification using VMM HAL-SCEMI On ChipIT Platform
(Monday, March 7, 2011)
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Introduction to SVA Assertions for Design Engineers
(Monday, March 7, 2011)
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CPUs in FPGAs: many faces to a trend
(Monday, March 7, 2011)
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STOP! Are You Gambling On Your Memory IP?
(Friday, March 4, 2011)
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Expediting processor verification through testbench infrastructure reuse
(Thursday, March 3, 2011)
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Adding encryption to disk drives is made easy using an IP core
(Thursday, March 3, 2011)
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Think static analysis cures all ills? Think again.
(Wednesday, March 2, 2011)
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Mixed-Signal = Analog + Digital, or is there more to it?
(Tuesday, March 1, 2011)
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CoreMark: A realistic way to benchmark CPU performance
(Tuesday, March 1, 2011)
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Key factors for success in dealing with Asian fabs
(Monday, February 28, 2011)
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MIPIâ„¢ MPHY - An introduction
(Monday, February 28, 2011)
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Cortex-M And Classical Series ARM Architecture Comparisons
(Monday, February 28, 2011)
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Virtual Channels Hardware Support in Switches in Relation to NoC Costs, Functions and Features
(Monday, February 21, 2011)
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Routing Congestion: The Growing Cost of Wires in Systems-on-Chip
(Monday, February 21, 2011)
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EDA focus shifts to system level design
(Wednesday, February 16, 2011)
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Ease production at 65nm with DFM
(Wednesday, February 16, 2011)
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Hardware Solutions to the Challenges of Multimedia IP Functional Verification
(Monday, February 14, 2011)
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Standard design constraints: The next productivity boost for custom design
(Monday, February 14, 2011)
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Integration Optimized SuperSpeed USB3.0 IP from Cadence - Delivering Superior Value to the SOC Designer
(Monday, February 14, 2011)
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Automatic shape-based routing to achieve parasitic constraint closure in custom design
(Thursday, February 10, 2011)
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Designing remote radio heads (RRHs) on high-performance FPGAs
(Tuesday, February 8, 2011)
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Hardware-based floating-point design flow
(Monday, February 7, 2011)
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The future is High-Level Synthesis
(Monday, February 7, 2011)
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Achieving first day multicore SoC software success
(Thursday, February 3, 2011)
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Using SystemC to build a system-on-chip platform
(Thursday, February 3, 2011)
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ESL anyone?
(Wednesday, February 2, 2011)
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7 myths of analog and mixed-signal ASIC design
(Friday, January 28, 2011)
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How to instrument your design with simple SystemVerilog assertions
(Thursday, January 27, 2011)
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Free I/O: Improving FPGA clock distribution control
(Monday, January 24, 2011)
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Multiband architecture for high-speed SerDes
(Thursday, January 20, 2011)
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How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
(Wednesday, January 19, 2011)
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Managing coverage grading in complex multicore microprocessor environments
(Wednesday, January 19, 2011)
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Using co-design to optimize system interconnect paths
(Monday, January 17, 2011)
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Designing an FPGA-based graphics controller
(Monday, January 17, 2011)
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Mixed-Signal Designs: The benefits of digital control of analog signal chains
(Monday, January 17, 2011)
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Scalable architectures for high-bandwidth Ethernet line cards
(Thursday, January 13, 2011)
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An RTL to GDSII approach for low power design: A design for power methodology
(Thursday, January 13, 2011)
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Is there a "one-size fits all" SOC PLL?
(Monday, January 10, 2011)
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When perfect is good enough
(Tuesday, January 4, 2011)
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Architecting hardware, software & communications for the electronic battlefield
(Tuesday, January 4, 2011)
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Configurable VESA - VGA and DVI Test Pattern Generator
(Monday, January 3, 2011)
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Understanding the basics of PLL frequency synthesis
(Monday, December 27, 2010)
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Only 10 days to shipping ... we may have a memory problem!
(Wednesday, December 22, 2010)
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