Design & Reuse
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2801 IP
2451
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
2452
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Two Port (1R1W) SRAM memory compiler....
2453
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
2454
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous high density Two Port (1R1W) SRAM memory compiler....
2455
0.118
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous low density Low Power Two Port (1R1W) SRAM memory compiler....
2456
0.118
Two Port Register File Compiler IP, UMC 28nm HLP process
UMC 28nm HLP/ Low-K Two Port Register File compiler....
2457
0.118
Two Port Register File Compiler IP, UMC 28nm HLP process
UMC 28nm HLP peripheral LVT Two Port Register File memory compiler....
2458
0.118
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic Two Port Register File memory compiler....
2459
0.118
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/LVT process, Two Port Register File with LVT....
2460
0.118
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP Two Port Register File with Sleep/Retention/Nap mode feature....
2461
0.118
Two Port Register File Compiler IP, UMC 55nm LP process
UMC 55nm LP Logic process Synchronous Two Port Register File memory compiler....
2462
0.118
Two Port Register File Compiler IP, UMC 55nm LP process
UMC 55nm LP/ Low-K process PG Two Port Register File compiler....
2463
0.118
Two Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP/RVT and HVT Low-K Logic process synchronous ultra high density/6T cell Two Port Register File memory compiler....
2464
0.118
Two Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP Low-K Logic process synchronous Two Port Register File memory compiler....
2465
0.118
Two Port Register File Compiler IP, UMC 65nm LL process
UMC 65nm LL/RVT Low-K Logic process synchronous high density Two Port Register File SRAM memory compiler....
2466
0.118
Two Port Register File Compiler IP, UMC 65nm SP process
UMC 0.65um SP/RVT Low-K Logic process synchronous Two Port Register File memory compiler....
2467
0.118
Two Port Register File Compiler IP, UMC 90nm LL process
UMC 90nm LL/RVT Synchronous high density Two Port Register File memory compiler....
2468
0.118
Two Port Register File Compiler IP, UMC 90nm SP process
UMC 90nm Standard Performance Low-K process Two Port SRAM Register File compiler....
2469
0.118
Two Port Register File Compiler IP, UMC 90nm SP process
UMC 90nm SP Logic Low-K process synchronous Two Port (1R1W) Register File SRAM memory compiler....
2470
0.0
A 200Mbps 0.9V SLVS Transceiver in TSMC 22nm
This SLVS I/O Library, implemented in TSMC 22nm with an 11P7M_5X1Z UT-AlRDL metal stack, provides a 0.9V differential transceiver optimized for low-po...
2471
0.0
A 200Mbps 1.2V SLVS Transceiver in UMC 110
This library delivers a compact and reliable 1.2V SLVS transceiver solution in UMC 110nm, optimized for high-speed, low-power applications. Featuring ...
2472
0.0
1 Gbps DDR LVDS transmitter
065TSMC_LVDS_05 includes signal pins (INp and INn) to transmit data, and control pin EN_TX to configure the state of the transmitter. There are other ...
2473
0.0
1 Gbps DDR rail to rail LVDS receiver
LVDS_RX is LVDS receiver with rail to rail input range. The interface to the core logic includes the output signal pins (OUTp, OUTn) to receive data a...
2474
0.0
1 Gbps LVDS Transmitter
The interface to the core logic includes signal pin (INP) to transmit data and control pin ( EN) to configure the state of the transmitter. There are ...
2475
0.0
1 Gbps Rail to Rail LVDS receiver
065TSMC_LVDS_08 is LVDS receiver with rail to rail input range. The interface to the core logic includes the output signal pins (OUTP, OUTN) to receiv...
2476
0.0
2 Gbps Rail to Rail LVDS receiver
065TSMC_LVDS_10 is LVDS receiver with rail to rail input range. EN_T enables 100 Ohm internal resistor. The CAL_T adjusts 100 Ohm internal resistor, t...
2477
0.0
A GlobalFoundries 28nm ESD Library
This ESD library is a silicon-proven set of discrete, pad-independent ESD clamps for GlobalFoundries 28nm technology. The library is designed to provi...
2478
0.0
1 Port High-Current Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option
1 Port Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option...
2479
0.0
2 Port High-Density Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option
2 Port High-Density Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option...
2480
0.0
1 Port Multi-Bank Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option
1 Port Multi-Bank Register File Compiler with Column Redundancy, Low Leakage with retention, Power Gating w/wo retention, Dual Rail, Mixed VT option...
2481
0.0
7 track Extra Low Consumption standard cell library with Dual voltage capability
TSMC 152 G, SESAME eLC DV is specifically designed to enable robust dual voltage operation, with characterizations taking into account physical phenom...
2482
0.0
7 track Extra Low Consumption standard cell library with Dual Voltage capability
TSMC 180 RFID, SESAME eLC is specifically designed to enable Dual Voltage operation (1.8 V +/- 10% 1.1 V +/- 10%) and to operate near threshold volta...
2483
0.0
7 track Extra Low Consumption standard cell library with Dual voltage capability (1.8 V +/-10% / 1.1 V +/- 10%)
TSMC 180 BCD, SESAME eLC DV is specifically designed to enable robust dual voltage operation, with characterizations taking into account physical phen...
2484
0.0
7 track Extra Low Consumption standard cell library with Dual voltage capability (1.8 V / 1.1 V)
TSMC 180 G, SESAME HD DV optimized for high density and low power, with characterizations taking into account physical phenomena linked to low voltage...
2485
0.0
6 track High Density standard cell library at TSMC 180 nm
TSMC 180 G, SESAME HD provides the best trade-off between area and power achieved from an innovative cell design enabling 6-track cells....
2486
0.0
6 track High Density standard cell library at TSMC 180 nm
Foundry Sponsored, TSMC 180 eLL, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-tr...
2487
0.0
6 track High Density standard cell library at TSMC 180 nm
TSMC 180 uLL, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-track cells and 1P3M ...
2488
0.0
6 track High Density standard cell library at TSMC 180nm
TSMC 180 RF, SESAME HD optimized for high density and low power, RF models...
2489
0.0
6 track High Density standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 uLP, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-tra...
2490
0.0
6 track High Density standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 uLPeF, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-t...
2491
0.0
9 track Near Threshold Voltage standard cell library at TSMC 55 nm
TSMC 55 uLPeF, SESAME NTV, an extreme low voltage library designed to operate down to the minimum data retention voltage allowing users to share the s...
2492
0.0
8 track thick oxide standard cell library at TSMC 130 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
TSMC 130 G, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the ...
2493
0.0
9 track thick oxide standard cell library at TSMC 180 - low leakage and direct battery connection (operating voltages from 1.62 V to 3.63 V)
TSMC 180 G, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the ...
2494
0.0
9 track thick oxide standard cell library at TSMC 180 - low leakage and direct battery connection (operating voltages from 1.62 V to 3.63 V)
TSMC 180 RF, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the...
2495
0.0
6 track Ultra High Density standard cell library at TSMC 130 nm
Foundry Sponsored, TSMC 130 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spi...
2496
0.0
6 track Ultra High Density standard cell library at TSMC 130 nm
TSMC 130 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest a...
2497
0.0
6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest...
2498
0.0
6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest a...
2499
0.0
6 track Ultra High Density standard cell library at TSMC 55 nm
TSMC 55 LP, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest a...
2500
0.0
6 track Ultra High Density standard cell library at TSMC 90 nm with dual voltage capability
TSMC 90 uLL, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest ...