Design & Reuse
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2743 IP
2451
0.118
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/RVT Low-K Logic Two Port Register File memory compiler....
2452
0.118
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/LVT process, Two Port Register File with LVT....
2453
0.118
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP Two Port Register File with Sleep/Retention/Nap mode feature....
2454
0.118
Two Port Register File Compiler IP, UMC 55nm LP process
UMC 55nm LP Logic process Synchronous Two Port Register File memory compiler....
2455
0.118
Two Port Register File Compiler IP, UMC 55nm LP process
UMC 55nm LP/ Low-K process PG Two Port Register File compiler....
2456
0.118
Two Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP/RVT and HVT Low-K Logic process synchronous ultra high density/6T cell Two Port Register File memory compiler....
2457
0.118
Two Port Register File Compiler IP, UMC 55nm SP process
UMC 55nm SP Low-K Logic process synchronous Two Port Register File memory compiler....
2458
0.118
Two Port Register File Compiler IP, UMC 65nm LL process
UMC 65nm LL/RVT Low-K Logic process synchronous high density Two Port Register File SRAM memory compiler....
2459
0.118
Two Port Register File Compiler IP, UMC 65nm SP process
UMC 0.65um SP/RVT Low-K Logic process synchronous Two Port Register File memory compiler....
2460
0.118
Two Port Register File Compiler IP, UMC 90nm LL process
UMC 90nm LL/RVT Synchronous high density Two Port Register File memory compiler....
2461
0.118
Two Port Register File Compiler IP, UMC 90nm SP process
UMC 90nm Standard Performance Low-K process Two Port SRAM Register File compiler....
2462
0.118
Two Port Register File Compiler IP, UMC 90nm SP process
UMC 90nm SP Logic Low-K process synchronous Two Port (1R1W) Register File SRAM memory compiler....
2463
0.0
1 Gbps LVDS Transmitter
The interface to the core logic includes signal pin (INP) to transmit data and control pin ( EN) to configure the state of the transmitter. There are ...
2464
0.0
2 Gbps Rail to Rail LVDS receiver
065TSMC_LVDS_10 is LVDS receiver with rail to rail input range. EN_T enables 100 Ohm internal resistor. The CAL_T adjusts 100 Ohm internal resistor, t...
2465
0.0
7 track Extra Low Consumption standard cell library with Dual voltage capability
TSMC 152 G, SESAME eLC DV is specifically designed to enable robust dual voltage operation, with characterizations taking into account physical phenom...
2466
0.0
7 track Extra Low Consumption standard cell library with Dual Voltage capability
TSMC 180 RFID, SESAME eLC is specifically designed to enable Dual Voltage operation (1.8 V +/- 10% 1.1 V +/- 10%) and to operate near threshold volt...
2467
0.0
7 track Extra Low Consumption standard cell library with Dual voltage capability (1.8 V +/-10% / 1.1 V +/- 10%)
TSMC 180 BCD, SESAME eLC DV is specifically designed to enable robust dual voltage operation, with characterizations taking into account physical phen...
2468
0.0
7 track Extra Low Consumption standard cell library with Dual voltage capability (1.8 V / 1.1 V)
TSMC 180 G, SESAME HD DV optimized for high density and low power, with characterizations taking into account physical phenomena linked to low voltage...
2469
0.0
6 track High Density standard cell library at TSMC 180 nm
TSMC 180 G, SESAME HD provides the best trade-off between area and power achieved from an innovative cell design enabling 6-track cells....
2470
0.0
6 track High Density standard cell library at TSMC 180 nm
Foundry Sponsored, TSMC 180 eLL, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-tr...
2471
0.0
6 track High Density standard cell library at TSMC 180 nm
TSMC 180 uLL, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-track cells and 1P3M ...
2472
0.0
6 track High Density standard cell library at TSMC 180nm
TSMC 180 RF, SESAME HD optimized for high density and low power, RF models...
2473
0.0
6 track High Density standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 uLP, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-tra...
2474
0.0
6 track High Density standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 uLPeF, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-t...
2475
0.0
9 track Near Threshold Voltage standard cell library at TSMC 55 nm
TSMC 55 uLPeF, SESAME NTV, an extreme low voltage library designed to operate down to the minimum data retention voltage allowing users to share the s...
2476
0.0
8 track thick oxide standard cell library at TSMC 130 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
TSMC 130 G, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the ...
2477
0.0
9 track thick oxide standard cell library at TSMC 180 - low leakage and direct battery connection (operating voltages from 1.62 V to 3.63 V)
TSMC 180 G, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the ...
2478
0.0
9 track thick oxide standard cell library at TSMC 180 - low leakage and direct battery connection (operating voltages from 1.62 V to 3.63 V)
TSMC 180 RF, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the...
2479
0.0
8 track thick oxide standard cell library at TSMC 90 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
TSMC 90 LPeF, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through th...
2480
0.0
8 track thick oxide standard cell library at TSMC 90 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
TSMC 90 LP, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the ...
2481
0.0
8 track thick oxide standard cell library at TSMC 90 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
TSMC 90 uLL, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the...
2482
0.0
6 track Ultra High Density standard cell library at TSMC 130 nm
Foundry Sponsored, TSMC 130 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spi...
2483
0.0
6 track Ultra High Density standard cell library at TSMC 130 nm
TSMC 130 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest a...
2484
0.0
6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 BCD, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest...
2485
0.0
6 track Ultra High Density standard cell library at TSMC 180 nm
TSMC 180 G, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest a...
2486
0.0
6 track Ultra High Density standard cell library at TSMC 55 nm
TSMC 55 LP, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest a...
2487
0.0
6 track Ultra High Density standard cell library at TSMC 90 nm with dual voltage capability
TSMC 90 uLL, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest ...
2488
0.0
6 track Ultra High Density standard cell library at TSMC 90 nm with dual voltage capability
TSMC 90 LPeF, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest...
2489
0.0
V-by-One Tx IP, Silicon Proven in SMIC 40LL
V-by-One HS technology targets a high-speed data transmission of video signals based on the internal connection of equipment. V-by-One® HS Standard de...
2490
0.0
3.125 Gbps DDR 1-channel CML transmitter
065TSMC_CML_02 core logic interface includes signal pins (INP1, INP2 and INN1, INN2) for data transmission, control pin EN_TX to configure transmitter...
2491
0.0
3.125 Gbps DDR CML receiver
065TSMC_CML_01 core logic interface includes complementary output signal pins (OUTp, OUTn) for data transmission and enable pin EN_RX. PAD_INP and PAD...
2492
0.0
1.2 Gbps LVDS transmitter/receiver
The interface to the core logic in receiver mode includes the signal pins (out_p and out_n) to receive data and the control pins (en_rx, ten, t_cal ar...
2493
0.0
1.25 Gbps 4-Channel LVDS Deserializer in Samsung 28FDSOI
The MXL-LVDS-RX-4CH is a high performance 4-channel LVDS Receiver implemented using digital CMOS technology. Both the serial and parallel data are org...
2494
0.0
1.25 Gbps LVDS IPs library
028TSMC_LVDS_01 is a library including: • Transmitter LVDS driver (TX_LVDS); • Receiver LVDS driver (RX_LVDS); • Reduced range link receiver LVDS...
2495
0.0
1.25 Gbps LVDS IPs library
040TSMC_LVDS_01 is a library including: • Transmitter LVDS driver (LVDS_TX); • Receiver LVDS driver (LVDS_RX); • Reference current/voltage source (...
2496
0.0
3.3V Wide-Range General Purpose I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along with corner and spac...
2497
0.0
3.3V Wide-Range General Purpose I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core power, and analog power...
2498
0.0
3.3V Wide-Range General Purpose Inline I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core power, and analog power...
2499
0.0
7.5 Gbps DDR CML IPs library
040TSMC_CML_01 is a library including: • CML receiver (CML_RX); • CML transmitter (CML_TX). • Reference current/voltage source (CML_RS); • Refe...
2500
0.0
2.5V 5V Tolerant GPIO Inline IO Pad Set
The 3.3V General Purpose I/O (5VT) library provides programmable bidirectional I/O’s that are both 5V tolerant and fault tolerant. The I/O’s are prov...