Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow AMBA AHB / APB/ AXI (203)
arrow CXL (21)
arrow D2D (1)
arrow Gen-Z (6)
arrow HDMI (88)
arrow I2C (96)
arrow Interlaken (3)
arrow MIL-STD-1553 (3)
arrow MIPI (507)
arrow Multi-Protocol PHY (33)
arrow PCI (240)
arrow RapidIO (6)
arrow SAS (5)
arrow SATA (74)
arrow Serdes (106)
arrow Smart Card (3)
arrow USB (404)
arrow V-by-One (22)
arrow VESA (80)
arrow Other (36)
203 IP
1
50.0
AHB Octal SPI Controller with PSRAM and XIP Support
The Silvaco Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, usually an ind...
2
45.0
FlexNoC® 5 Interconnect IP
FlexNoC® Interconnect IP by Arteris is used by the world’s top semiconductor design teams as the backbone for on-chip communications in chips that tar...
3
25.0
I3C Advanced Controller, V1.1
I3C is a new a standard from the MIPI Alliance that unifies and extends the legacy interfaces of I2C and SPI and adds new powerful features to sup...
4
25.0
I3C Advanced Controller, V1.1 Lite
The I3C Advanced Controller Lite is a highly configurable I3C controller that can be used in microcontroller-based environments to provide I3C con...
5
25.0
I3C Advanced Target, V 1.1 Lite
The I3C Advanced Target Lite is a highly configurable I3C Target that can be used in microcontroller based environments to provide I3C connectivit...
6
25.0
I3C Advanced Target, V1.1
The I3C Advanced Target is a highly configurable I3C Target that can be used in microcontroller based environments to provide I3C connectivity to ...
7
25.0
I3C Autonomous Target, V1.1
The I3C Autonomous Target is intended for simple, data acquisition types of applications where a microprocessor is not needed to process the data....
8
25.0
Flash SPI controller master/slave
Veriest's SPI Master Controller IP provides an industry standard data communication channel between the AMBA APB and SPI buses. It supports SPI master...
9
16.0
AHB-Lite APB4 Bridge
The Roa Logic AHB-Lite APB4 Bridge is a fully parameterized soft IP interconnect bridge between the AMBA 3 AHB-Lite v1.0 and AMBA APB v2.0 bus protoco...
10
16.0
AHB-Lite General Purpose Memory Module
The Roa Logic AHB-Lite Memory IP is a fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Master. All signals defi...
11
16.0
AHB-Lite Multilayer Switch
The Roa Logic AHB-Lite Multi-layer Interconnect is a fully parameterized High Performance, Low Latency Interconnect Fabric soft IP for AHB-Lite. It al...
12
16.0
AHB-Lite Timer
The Roa Logic AHB-Lite Timer IP is a fully parameterized soft IP implementing a user-defined number of timers and functions as specified by the RISC-V...
13
16.0
RISC-V Compliant Platform Level Interrupt Controller
Fully Parameterized & Programmable Platform Level Interrupt Controller (PLIC) for RISC-V based Processor Systems supporting a user-defined number of i...
14
16.0
APB4 General Purpose Input/Output Module
The APB4 GPIO Core is fully parameterised core designed to provide a user-defined number of general purpose, bidirectional IO to a design. The IO a...
15
16.0
APB4 Multiplexer
The AMBA APB v2.0 bus protocol – commonly referred to as APB4 – defines a low-cost interface that is optimized for minimal power consumption and redu...
16
15.0
120dB PDM-to-PCM Digital Microphone Interface
The AR36T05 is a soft macro low-power high-performance digital microphone interface modulator IP. The IP converts stereo/mono 1-bit pulse-density modu...
17
12.0
105dB PCM-to-PDM Stereo Converter
The AR37T01 is a digitally coded stereo PCM-to-PDM conversion IP with 8-bit pattern-code programming. The IP translates parallel PCM input data in...
18
11.0
DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Command Stream List
The Digital Blocks DB-DMAC-MC2-CS-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memo...
19
11.0
DMA AXI4-Stream to/from AXI4 Memory Map - Scatter-Gather Descriptor List
The Digital Blocks DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memo...
20
10.0
AHB Multi Fabric
The AHB Fabric provides the necessary infrastructure to connect up to 16 shared AHB Slaves to up to 16 AHB-Lite Bus Masters. The off-the-self configu...
21
10.0
AHB QSPI Controller with Execute in Place (XIP)
The Quad Serial Peripheral Interface (OSPI) core is a serial data link (SPI) master which controls an external serial FLASH device. Reading and wri...
22
10.0
AMBA AHB Target
AMBA AHB is a bus interface designed for high-performance synthesizable applications. It specifies the interface between components such as initiator ...
23
10.0
AMBA APB Target
Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is desi...
24
10.0
AMBA AXI Target
The "advanced extensible interface" (AXI) bus is a high-performance parallel bus that connects on-chip peripheral circuits (or IP blocks) to processor...
25
10.0
ONFI 3.2 NAND Flash Controller
The Arasan ONFI 3.2 compliant NAND Flash Controller IP Core is a full featured, easy to use, synthesizable design that is easily integrated into any S...
26
10.0
IP Solutions for the AMBA Interconnect
The Synopsys IP solutions for the ARM® AMBA® interconnect include synthesizable IP, verification IP (VIP) and automated assembly with Synopsys’ coreAs...
27
10.0
AXI QSPI with Execute in Place
The Quad Serial Peripheral Interface module either controls a serial data link as a master, or reacts to a serial data link as a slave. The IPC...
28
7.0
Display Controller - LCD / OLED Panels (AHB Bus)
The Digital Blocks DB9000AHB TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 2.0 AHB Bus to a TFT LCD pane...
29
7.0
Display Controller - LCD / OLED Panels (AHB-Lite Bus)
The Digital Blocks DB9000AHB-Lite TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 3.0 AHB-Lite Bus V1.0 to...
30
6.0
AHB To PCI Wrapper
VinChip’s AHB to PCI wrapper can be used to verify AHB (AMBA) based systems on a PCI environment for ease of debugging the target hardware and it can ...
31
6.0
AHB2APB Bridge IP
Truechip's AHB2APB Bridge IP provides chip designers and architects, an efficient way to connect Different Bus Protocol based IPs with reduced latency...
32
6.0
CHI2AXI bridge IP
The CHI2AXI bridge is a high-performance protocol converter designed to enable seamless interoperability between CHI (Coherent Hub Interface) and AXI ...
33
6.0
TileLink2AXI Bridge IP
The TileLink2AXI Bridge is a synthesizable, high-performance IP designed to provide seamless interoperability between TileLink-based components and AM...
34
6.0
AXI Expander IP
The Truesilicon AXI Expander Block is a configurable IP designed for AXIbased systems where the data width of the Master Interface (MI) is smaller tha...
35
6.0
AXI Splitter IP
The AXI Splitter is a configurable IP designed to enable seamless data width conversion in AMBA AXI-based systems. It is primarily used when a wide da...
36
6.0
AXI- Interconnect : Advanced Extensible Interface Bus IP
The AMBA AXI protocol is targeted at high-performance, high-frequency system designs and includes a number of features that make it suitable for high-...
37
6.0
AXI2APB Bridge
Truechip's AXI2APB IP provides chip designers and architects, an efficient way to connect AXI & APB based IPs with reduced latency, power, and area....
38
6.0
AXI2APB Bridge IP
The TrueSilicon's AXI to APB Bridge is a high-performance protocol converter IP designed to enable seamless communication between AXI master devices a...
39
6.0
AXI2CHI Bridge IP
The AXI2CHI bridge is a high-performance protocol converter that enables seamless integration between AXI (Advanced eXtensible Interface) and CHI (Coh...
40
6.0
AXI2TileLink Bridge IP
The AXI2TileLink Bridge is a high-performance, synthesizable IP designed to enable seamless interoperability between AMBA AXI-based subsystems and Til...
41
5.0
I2C Master Serial Interface Controller
The CC-I2C_MST-APB is a synthesisable Verilog model of a I2C serial interface controller. The I2C core can be efficiently implemented on FPGA and ASIC...
42
5.0
UART Serial Interface Controller
The CC-UART-APB is a synthesisable Verilog model of a UART serial interface controller. The UART core can be efficiently implemented on FPGA and ASIC ...
43
5.0
PDM-to-PCM Conversion with AMBA Interface
The AR36T01 is a soft macro low-power digital microphone interface modulator IP. The IP converts stereo/mono 1-bit pulse-density modulated (PDM) bit s...
44
5.0
Advanced Encryption Standard Module
The CC-AES-APB is a synthesisable Verilog model of a Advanced Encryption Standard module. The AES core can be efficiently implemented on FPGA and ASIC...
45
5.0
General Purpose Input/Output Controller
The CC-GPIO-APB is a synthesisable Verilog model of a General Purpose Input/Output Controller. The GPIO core can be efficiently implemented on FPGA an...
46
5.0
General Purpose Input/Output Controller
The CC-GPIO-AXI is a synthesisable Verilog model of a General Purpose Input/Output Controller. The GPIO core can be efficiently implemented on FPGA an...
47
5.0
Peripheral Direct Memory Access Controller
The CC-PDMA-APB-AHB is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on ...
48
5.0
Peripheral Direct Memory Access Controller
The CC-PDMA-AXI-AXI is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on ...
49
5.0
AHB Cache Controller Core
The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave AHB processor interface and a 32-bit master AHB interface to the...
50
5.0
Configurable System Tick Counter
The CC-SYSTICK-APB is a synthesisable Verilog model of a system tick timer counter controller. The SYSTICK core can be efficiently implemented on FPGA...