Design & Reuse
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480 IP
51
20.0
I3C Dual Controller
The Arasan I3C Secondary Controller IP Core implements Active controller functionality as defined by the MIPI Alliance’s I3C Specification and Seconda...
52
20.0
MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
53
20.0
MIPI C-PHY v1.0 D-PHY v1.2 RX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
54
20.0
MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm,N6, N5)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
55
20.0
MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
56
20.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm, 12nm, N5)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
57
20.0
MIPI C-PHY/D-PHY Combo(5nm, 7nm, 12/16nm, 28nm, 40nm, 55nm)
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...
58
20.0
MIPI CSI-2 host/device controllers for high-speed serial interface between image processor and camera sensors
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...
59
20.0
MIPI CSI-2 Tansmitter v 1.3, C-PHY compatible
The MIPI Camera Serial Interface (CSI-2) Transmitter, typically resides in a mobile platform’s camera module, and communicates over a D-PHY/C-PHY link...
60
20.0
MIPI D-PHY Bidirectional 2 Lanes in GF (40nm, 28nm, 22nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
61
20.0
MIPI D-PHY Bidirectional 2 Lanes in SMIC (40nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
62
20.0
MIPI D-PHY Bidirectional 2 Lanes in TSMC (40nm, 28nm, 16nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
63
20.0
MIPI D-PHY Bidirectional 4 Lanes in Fujitsu (40nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
64
20.0
MIPI D-PHY Bidirectional 4 Lanes in GF (40nm, 28nm, 22nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
65
20.0
MIPI D-PHY Bidirectional 4 Lanes in SMIC (40nm, 28nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
66
20.0
MIPI D-PHY Bidirectional 4 Lanes in TSMC (40nm, 28nm, 16nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
67
20.0
MIPI D-PHY RX
Silicon Library's MIPI DPHY 1.2 Rx PHY IP supports data rates up to 1.5Gbps. This IP includes two PLLs. This silicon proven IP is available in variou...
68
20.0
MIPI D-PHY Rx-Only 2 Lanes in GF (28nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
69
20.0
MIPI D-PHY Rx-Only 2 Lanes in SMIC (40nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
70
20.0
MIPI D-PHY Rx-Only 2 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
71
20.0
MIPI D-PHY Rx-Only 2 Lanes in UMC (28nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
72
20.0
MIPI D-PHY Rx-Only 4 Lanes in GF (28nm, 12nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
73
20.0
MIPI D-PHY Rx-Only 4 Lanes in SMIC (40nm, 28nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
74
20.0
MIPI D-PHY Rx-Only 4 Lanes in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, N7, N6)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
75
20.0
MIPI D-PHY Rx-Only 4 Lanes in UMC (28nm, 22nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
76
20.0
MIPI D-PHY TX
Silicon Library's MIPI DPHY 1.2 Tx PHY IP supports data rates up to 1.5Gbps and 2.5Gbps per lane (in HS), depending on the technology node. This sili...
77
20.0
MIPI D-PHY Tx-Only 2 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
78
20.0
MIPI D-PHY Tx-Only 4 Lanes in GF (12nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
79
20.0
MIPI D-PHY Tx-Only 4 Lanes in SMIC (28nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
80
20.0
MIPI D-PHY Tx-Only 4 Lanes in TSMC (28nm, 22nm, 16nm, 12nm, N7, N6)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
81
20.0
MIPI D-PHY Tx-Only 4 Lanes in UMC (28nm, 22nm)
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
82
20.0
MIPI DSI-2 controllers with VESA DSC for high-speed serial interface between application processor and displays
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...
83
20.0
MIPI DSI-2 host/device controllers for high-speed serial interface between application processor and displays
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...
84
20.0
MIPI I3C controller delivers high bandwidth and scalability for integration of multiple sensors
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...
85
20.0
MIPI M-PHY G4 Type 1 1Tx1RX in TSMC (16nm, 12nm, N5)
The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v5.0 specification, supports speeds up to 23.32 Gbps per lane. The I...
86
20.0
MIPI M-PHY G4 Type 1 2TX2RX in GF (12nm)
The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v5.0 specification, supports speeds up to 23.32 Gbps per lane. The I...
87
20.0
MIPI M-PHY G5 Type 1 2Tx2Rx in Samsung (14nm)
The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v5.0 specification, supports speeds up to 23.32 Gbps per lane. The I...
88
20.0
MIPI M-PHY v4.1/v3.1 IP in TSMC(5nm, 6nm, 7nm, 12nm,16nm, 22nm, 28nm, 40nm, and 55nm)
MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pi...
89
20.0
MIPI UniPro IP for reliable, high-performance and low power link between devices in mobile devices
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...
90
15.0
2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Transmitter
The SVTPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps. The highly parallel architecture of t...
91
15.0
I3C Device Controller v1.2
The Arasan I3C Device Controller IP Implements Device Controller functionality as defined by the MIPI Alliance’s I3C Specification. The I3C bus is us...
92
15.0
I3C Dual Controller v1.2
The Arasan I3C Secondary Controller IP Core implements Active controller functionality as defined by the MIPI Alliance’s I3C Specification and Seconda...
93
15.0
High Performance Second Generation Extended MIPI CSI2 Receiver
Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps. This development requires high bandwidth betwee...
94
15.0
MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
The SVTPlus-CSI2-F is a second generation MIPI CSI2-Tx transmitter IP core for FPGA implementations. It complies with MIPI® CSI2 V2.0 and DPHY1.2 spec...
95
15.0
MIPI I3C Controller and Target fully featured IP solution
The MIPI I3C Controller IP is a highly optimized and technology-agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both ASIC and F...
96
15.0
Multi-Video-Source Multiplexing Serial Video Transmitter for MIPI CSI2
The SVT-CS4AP2 supports MIPI CSI2 over MIPI D-PHY. It allows mutilplexing of up to 10 video sources into a CSI2 output stream...
97
15.0
Extended MIPI CSI2 Serial Video Receiver, 64 bits, 8 data lanes, 4 pixels/clock
Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps. This development requires high bandwidth betwee...
98
14.0
I3C Controller
Controller IP for the MIPI I3C interface The Cadence® IP Family for MIPI® Protocols delivers area-optimized interface IP with the low power and high ...
99
14.0
MIPI CSI-2 RX Controller for v2.1
CSI-2 receiver controller for application processor The Cadence® Receiver (RX) Controller IP for MIPI® Camera Serial Interface 2 (CSI-2SM) is respons...
100
14.0
MIPI CSI-2 TX Controller for v2.1
CSI-2 transmitter controller for application processor The Cadence® Transmitter (TX) Controller IP for MIPI DSI is compliant with the MIPI® Alliance ...