Design & Reuse
arrow AMBA AHB / APB/ AXI (185)
arrow CXL (20)
arrow D2D (59)
arrow Gen-Z (6)
arrow HDMI (86)
arrow I2C (97)
arrow Interlaken (2)
arrow MIL-STD-1553 (3)
arrow MIPI (480)
arrow Multi-Protocol PHY (37)
arrow PCI (254)
arrow RapidIO (6)
arrow SAS (6)
arrow SATA (95)
arrow Smart Card (6)
arrow USB (391)
arrow V-by-One (22)
arrow VESA (72)
arrow Other (34)
480 IP
201
1.0
MIPI CSI2 Receiver Interface
The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile...
202
1.0
MIPI D-PHY Combo LVDS CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2, MIPI D-PHY, and LVDS protocols. The CSI-2 link protocol specification is a part of group of communication...
203
1.0
MIPI D-PHY Combo LVDS DSI TX IP
Innosilicon MIPI DSI Transmitter implements DSI, MIPI D-PHY, and LVDS protocol. The DSI link protocol specification is a part of group of communicatio...
204
1.0
MIPI D-PHY CSI-2 RX IP
Innosilicon CSI-2 Receiver implements MIPI CSI-2 protocol as well as D-PHY protocol. The CSI-2 link protocol specification is a part of group of commu...
205
1.0
MIPI D-PHY DSI 1.2G RX IP
Innosilicon MIPI DSI receiver implements the MIPI DSI as well as D-PHY protocols. The DSI link protocol specification is a part of group of communicat...
206
1.0
MIPI D-PHY DSI 1.5G RX IP
Innosilicon MIPI DSI RX IP implements the MIPI D-PHY as well as MIPI DSI protocols. The DSI link protocol specification is a part of group of communic...
207
1.0
MIPI D-PHY DSI TX IP
Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI D-PHY protocol. The DSI link protocol specification is a part of group of...
208
1.0
MIPI D-PHY TX
The Innosilicon MIPI D-PHY TX provides a MIPI® high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional ...
209
1.0
MIPI D-PHY TX COMBO LVDS PHY
The Innosilicon MIPI D-PHY TX combo LVDS PHY integrates a D-PHY and a LVDS in a single IP core, which provides a MIPI® high speed data plus low-power ...
210
1.0
MIPI D-PHY TX Combo TTL PHY
The Innosilicon MIPI D-PHY TX provides a MIPI® high speed data plus low-power low speed transmitter that supports data transfer in the bi-directional ...
211
1.0
MIPI D-PHY TX/CSI2 Link Controller
CD12631S4TIP is a link IP that allows you to link a camera module or CMOS image sensor (CIS) to a host system. This LINK IP is a soft macro IP that h...
212
1.0
MIPI D-PHY/sub-LVDS combo Transmitter 1.5G/1.0Gbps 4-Lane
The CL12661K4T1AM2JIP is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System. The CL12661K4T1AM2JIP is designed to support...
213
1.0
MIPI D-PHY_1.2G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
214
1.0
MIPI D-PHY_1.5G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
215
1.0
MIPI D-PHY_2.5G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
216
1.0
MIPI D-PHY_4.5G CSI-2 RX IP
Innosilicon CSI-2 Receiver implements CSI-2 protocol and MIPI D-PHY protocol. The CSI-2 link protocol specification is a part of group of communicatio...
217
1.0
MIPI DPHY DSI TX IP
Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI D-PHY protocol. The DSI link protocol specification is a part of group of...
218
1.0
MIPI DPHY1.2 RX (support combo TTL, LVDS, HiSPI)
The Innosilicon MIPI D-PHY IP provides D-PHY in a single IP core. It integrates a compatible PHY that supports high speed data receiver, plus a MIPI® ...
219
1.0
MIPI DPHY2.0/CPHY1.1 TX (support combo TTL, LVDS, HiSPI)
The Innosilicon MIPI C/D PHY TX integrates a MIPI C-PHY and a MIPI D-PHY in a single IP core, which provides a MIPI high speed data plus low-power low...
220
1.0
MIPI DSI-2 DSC RX IP
Innosilicon MIPI DSI-2 DSC RX IP implements the MIPI C/D-PHY as well as MIPI DSI-2 protocols and contains the DSC (Display Stream Compression) algorit...
221
1.0
MIPI HSI Controller - (High-Speed Synchronous Serial Interface)
The High Speed Synchronous Serial Interface (HSI) Controller is used to provide high bandwidth, point-to-point, serial communication between two peers...
222
1.0
MIPI LLI Controller - (Low Latency Interface)
The Low Latency interface (LLI) is a point-to point-interconnect that allows two devices on the separate chips to communicate as if a device attached ...
223
1.0
MIPI M-PHY
INNOSILICON™ M-PHY IP implements the MIPI M-PHY protocol V4.1. The M-PHY protocol specification is a part of a group of communication protocols define...
224
1.0
MIPI RFFE Master Controller IP Core
Mobile radio communication is trending towards complex multi-radio systems comprising of several transceivers. The MIPI RFFE bus is is 2-wire serial i...
225
1.0
MIPI RFFE Slave Controller IP Core
Mobile radio communication is trending towards complex multi-radio systems comprising of several transceivers. The MIPI RFFE bus is is 2-wire serial i...
226
1.0
MIPI RFFE Slave Controller IP Core v3.0
Mobile radio communication is trending towards complex multi-radio systems comprising several transceivers. Arasan supports the latest MIPI RFFE stand...
227
1.0
MIPI SLIMbus Device Controller V2.0
The Arasan SLIMbus Device Controller IP is designed to provide MIPI SLIMbus 1.01 compliant connectivity for a peripheral device, like an audio codec, ...
228
1.0
MIPI SLIMbus Host Controller v2.0
The MIPI SLIMbus Host typically resides in a mobile platform’s application processor and provides two-wire, multi-drop connectivity with multiple audi...
229
1.0
MIPI SoundWire Master Controller 1.1
The Total MIPI Soundwire IP Solution enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package t...
230
1.0
MIPI SoundWire Slave Controller 1.1
The Total MIPI Soundwire IP Solution enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package t...
231
1.0
MIPI UniPro Controller - v1.6
To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to define and promote open...
232
1.0
MIPI UniPro Stack - v1.6
To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to define and promote open...
233
1.0
HLMC 55nm EF MIPI DPHY V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes. It can support both...
234
1.0
GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V1.0/V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v1.0 and D-PHY v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes. It c...
235
1.0
GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V2.1/V3.0
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of 1-Clock and 4-Data lanes. It can support Slav...
236
1.0
GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V2.1/V3.0
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of Bi-directional 1-Clock and 4-Data lanes. It c...
237
1.0
GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Slave V1.0/V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v1.0 and D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes. It can support Slav...
238
1.0
GLOBALFOUNDRIES 22nm FDX MIPI DPHY Master V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes. It can support Master side. Each...
239
1.0
GLOBALFOUNDRIES 22nm FDX MIPI DPHY Slave V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes. It can support Slave side. Each l...
240
1.0
SMIC 110nm MIPI DPHY
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes. It can support both...
241
1.0
SMIC 55nm LL MIPI DPHY
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.1”, which consists of Bi-directional 1-Clock and 4-Data lanes. It can support both...
242
1.0
Multi-PHY Receiver Link Controller
CD12842M8LRM3BM4AIP312P5 is a link IP that allows you to link a camera module or CMOS image sensor (CIS) to a host system. This LINK IP is a soft macr...
243
0.6098
MIPI D-PHY TRx 5nm
The MIPI D-PHY IP is a hardmacro PHY for CSI RX or DSI TX. IO pads and ESD structures are included. Extensive built-in self test features such as loop...
244
0.3729
Dolphin I3C Controller & PHY
DTI I3C Controller provides the logic consistent with NXP I3C specification to support the communication of low-speed integrated circuits through I3C ...
245
0.118
MIPI Controller IP, CSI-2 Receiver, High-Speed 80Mbps to 1.5Gbps per data lane, Soft IP
MIPI CSI Receiver Controller....
246
0.118
MIPI Controller IP, CSI-2 Transmitter, High-Speed 80Mbps to 1.5Gbps per data lane, Soft IP
MIPI Transmitter Controller....
247
0.118
MIPI Controller IP, DSI Host, Soft IP
DSI Host Controller....
248
0.118
MIPI Controller IP, DSI Peripheral, Soft IP
MIPI DSI Peripheral Controller....
249
0.118
MIPI CSI Receiver 1G/ SLVDS 1G /HiSPi 1G, 1.8V/3.3V GPI 100MHz; UMC 28nm HPC Logic Process
MIPI CSI Receiver 1G/ SLVDS 1G /HiSPi 1G, 1.8V/3.3V GPI 100MHz; UMC 28nm HPC Logic Process...
250
0.118
MIPI D-PHY Receiver IP, 80Mbps - 1.5Gbps, UMC 40nm LP process
MIPI Receiver 80Mbps-1.5Gbps, UMC 40nm LP Low-K Logic process....