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49 IP
1
200.0
MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
The MXL-CDPHY-6p0G-CSI-2-RX+-T-N6 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificat...
2
200.0
MIPI C-PHY/D-PHY Combo RX+ IP (4.5Gsps/4.5Gbps) in TSMC N5
The MXL-CD-PHY-CSI-RX+-T-N05 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...
3
200.0
MIPI C-PHY/D-PHY Combo Universal IP (8.0Gsps/trio, 6.5Gbps/lane) in TSMC 16FFC
The MXL-CDPHY-UNIV-8p0G-T-16FFC is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificatio...
4
102.0
MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 4.5Gsps/4.5Gbps
The MXL-CDPHY-4p5G-CSI-2-TX+-16FFC is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specifica...
5
102.0
MIPI C-PHY/D-PHY Combo RX IP 4.5Gsps/4.5Gbps in TSMC N7
The MXL-CDPHY-4p5G-CSI-2-RX-T-N7FF is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specific...
6
102.0
MIPI C-PHY/D-PHY Combo TX+ IP 4.5Gsps/4.5Gbps in TSMC N5
The MXL-CDPHY-DSI-TX+-T-N05 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification fo...
7
52.0
MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps
The MXL-CDPHY-3p5G-CSI-2-TX+-40LP is a high-frequency, low-power, low-cost, source synchronous, physical Layer supporting the MIPI Alliance Specificat...
8
52.0
MIPI C-PHY/D-PHY Combo DSI RX+ IP (4.5Gsps/trio, 6.5Gbps/lane) in TSMC 16FFC
The MXL-CD-PHY-DSIRX+-T-16FFC is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...
9
50.0
MIPI C-PHY v1.0 D-PHY v1.2 TX 2 trios/2 Lanes in TSMC (12nm, N5, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
10
50.0
MIPI C-PHY v1.0 D-PHY v1.2 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
11
50.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N4, N3E)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
12
50.0
MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N5, N4, N3E, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
13
50.0
MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N6, N5, N3)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
14
20.0
MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
15
20.0
MIPI C-PHY v1.0 D-PHY v1.2 RX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
16
20.0
MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm,N6, N5)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
17
20.0
MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
18
20.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm, 12nm, N5)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
19
11.0
MIPI C-PHY/D-PHY Combo 2-Lane CSI-2 TX+ IP in TSMC 40ULP
The MXL-CDPHY-2L-CSI-2-TX+-40ULP is a high-frequency, low-power, low-cost, sourcesynchronous, physical Layer supporting the MIPI Alliance Specificatio...
20
11.0
MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps
The MXL-CD-PHY-CSITX+-ST-28FDSOI is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificati...
21
11.0
MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 22ULP
The MXL-CDPHY-DSI-RX-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification f...
22
11.0
MIPI C-PHY/D-PHY Combo Universal IP, 4.5Gsps/4.5Gbps in TSMC 22ULP
The MXL-CD-PHY-UNIV-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification fo...
23
10.0
MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N5A, N3A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
24
7.0
MIPI RX PHY in SMIC28nm
MIPI RX PHY is a mass production IP for D-PHY v1.2 and C-PHY v1.2 protocols. It includes a total of 5 Lanes, among which there are 4 data lanes and 1...
25
3.0
MIPI C-PHY TRx 2.5Gsps) / D-PHY TRx 4.5Gbps Combo PHY (8nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...
26
1.0
GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V2.1/V3.0
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of Bi-directional 1-Clock and 4-Data lanes. It c...
27
1.0
Multi-PHY Receiver Link Controller
CD12842M8LRM3BM4AIP312P5 is a link IP that allows you to link a camera module or CMOS image sensor (CIS) to a host system. This LINK IP is a soft macr...
28
0.0
MIPI C-PHY TRx(80-8000Msps) / MIPI D-PHY TRx(80-9000Mbps) Combo PHY 4nm
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 9Gbps for D-PHY and 8Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Es...
29
0.0
MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in Samsung (SF2P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
30
0.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in Samsung (SF2P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
31
0.0
MIPI C-PHY v2.0 D-PHY v2.1 RX for TSMC N6
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
32
0.0
MIPI C-PHY v2.0 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (N7, N6)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
33
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) in TSMC 40ULP
The MXL-CDPHY-CSI-2-TX-T-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical layer supporting the MIPI Alliance Specification...
34
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) IP in TSMC 65LP
The MXL-CPHY-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as a MIPI Master support...
35
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX 3.5Gsps/trio in TSMC 28nm
The MXL-CDPHY-3p5G-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specifi...
36
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX 4.5Gsps/trio in TSMC 28nm
The MXL-CDPHY-4p5G-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specifi...
37
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps, 2T/2L
The MXL-CDPHY-CSI-2-TX+-40LP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification f...
38
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP in TSMC 40ULP
The MXL-CDPHY-CSI-2-TX+-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...
39
0.0
MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 28HPC+
The MXL-CPHY-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as MIPI Slave supporting c...
40
0.0
MIPI C-PHY/D-PHY Combo DSI TX (Transmitter) IP in TSMC 55G
The MXL-CPHY-DPHY-DSI-TX is a high-frequency low-power, high-performance, physical Layer. The PHY is configured as a MIPI Master supporting display in...
41
0.0
MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
The MXL-CPHY-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY can be configured as a MIPI Master or MIPI...
42
0.0
MIPI C/D COMBO RX HS PHY UMC 28/22nm
Our silicon-proven MIPI C- and D-PHY combo Rx PHY is compliant with Camera Serial Interface (CSI) version 1.2, supporting D-PHY speeds up to 4.5 GHz (...
43
0.0
MIPI C/D COMBO TX HS PHY UMC 28/22nm
The MIPI C/D combo PHY Tx IP is compliant with the Display Serial Interface (DSI) with D-PHY signaling up to 4.5GHz and C-PHY operating at a symbol ra...
44
0.0
MIPI C/D COMBO TX PHY, 5nm
The MIPI C/D combo PHY Tx IP is compliant with the Display Serial Interface (DSI) with D-PHY signaling up to 4.5GHz and C-PHY operating at a symbol ra...
45
0.0
MIPI C/D-PHY CSI-2 RX IP
Innosilicon CSI-2 Receiver implements MIPI CSI-2 as well as C/D-PHY protocols. The CSI-2 link protocol specification is a part of group of communicati...
46
0.0
MIPI C/D-PHY RX
The Innosilicon MIPI C/D-PHY RX provides D-PHY and C-PHY in a single IP core. It integrates a compatible PHY that supports high speed data receiver, p...
47
0.0
MIPI DSI-2 DSC RX IP
Innosilicon MIPI DSI-2 DSC RX IP implements the MIPI C/D-PHY as well as MIPI DSI-2 protocols and contains the DSC (Display Stream Compression) algorit...
48
0.0
Synopsys MIPI C-PHY IP on TSMC N7
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
49
0.0
Synopsys MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes for TSMC N5
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
