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220 IP
1
200.0
MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
The MXL-CDPHY-6p0G-CSI-2-RX+-T-N6 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificat...
2
200.0
MIPI C-PHY/D-PHY Combo RX+ IP (4.5Gsps/4.5Gbps) in TSMC N5
The MXL-CD-PHY-CSI-RX+-T-N05 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...
3
102.0
MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 4.5Gsps/4.5Gbps
The MXL-CDPHY-4p5G-CSI-2-TX+-16FFC is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specifica...
4
102.0
MIPI C-PHY/D-PHY Combo TX+ IP 4.5Gsps/4.5Gbps in TSMC N5
The MXL-CDPHY-DSI-TX+-T-N05 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification fo...
5
100.0
MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
Arasan's MIPI C-PHY is designed and compliant with latest MIPI C-Phy Standards. The MIPI C-PHY V1.2 improves throughput over a bandwidth-limited ch...
6
100.0
MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
Combination MIPI CPHY-DPHY Analog Interface The MIPI C-PHY V1.2 improves throughput over a bandwidth limited channel, allowing more data without in...
7
100.0
MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
Arasan delivers you MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete G...
8
100.0
Globalfoundries 12nm MIPI D-PHY V1.2@2.5GHz
Arasan Chip Systems announces the immediate availability of its MIPI D-PHY(SM) Globalfoundries 12nm FinFET process nodes. Arasan's D-PHY Global Foun...
9
80.0
MIPI D-PHY Rx IP, Silicon Proven in TSMC 22ULP
The MIPI D-PHY Analog RX IP Core is fully compliant to the D-PHY specification version 1.2. It supports the MIPI Camera Serial Interface (CSI-2) and D...
10
52.0
MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps
The MXL-CDPHY-3p5G-CSI-2-TX+-40LP is a high-frequency, low-power, low-cost, source synchronous, physical Layer supporting the MIPI Alliance Specificat...
11
52.0
MIPI D-PHY CSI-2 RX (Receiver) in GlobalFoundries 22FDX
The MXL-D-PHY-CSI-2-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Specification for D-PH...
12
50.0
UFS 4.0 Host Controller compatible with M-PHY 5.0 and UniPro 2.0
The Arasan UFS Host -UniPro IP is a simple, high performance, serial interface used primarily in mobile systems between host processing and NVM mass s...
13
50.0
MIPI D-PHY Rx IP, Silicon Proven in TSMC 28HPC+
The MIPI D-PHY Rx IP Core in 28HPC+ aligns precisely with the D-PHY specification version 1.2, facilitating support for the Display Serial Interface (...
14
50.0
MIPI D-PHY Tx IP, Silicon Proven in TSMC 22ULP
The MIPI D-PHY Analog TX IP Core adheres fully to version 1.2 of the D-PHY specification. It supports both the MIPI Camera Serial Interface (CSI-2) an...
15
40.0
MIPI D-PHY Rx IP, Silicon Proven in TSMC 12FFC
Several production nodes employ C-PHY/D-PHY Combo with the least amount of power and expense. To accommodate a range of applications, users can config...
16
30.0
UFS Host Controller 4.1 IP
The UFS Host Controller Interface (UFSHCI) is a high-performance interface that connects to UniPro and M-PHY IP in mobile platforms. It provides comma...
17
25.0
MIPI C-PHY v1.1
Combination MIPI CPHY-DPHY Analog Interface The MIPI C-PHY V1.0 improves throughput over a bandwidth limited channel, allowing more data without in...
18
25.0
MIPI C-PHY V1.1 TSMC 28nm HPC+
Combination MIPI CPHY-DPHY Analog Interface The MIPI C-PHY V1.1 improves throughput over a bandwidth limited channel, allowing more data without in...
19
25.0
MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+
Combination MIPI CPHY-DPHY Analog Interface The MIPI C-PHY V1.0 improves throughput over a bandwidth limited channel, allowing more data without in...
20
25.0
MIPI D-PHY V1.2@2.5GHz TSMC28nm HPC+
Arasan has the industry’s broadest portfolio of foundry and process technology support for MIPI D-PHY in the industry. The MIPI D-PHY analog IP is ava...
21
23.0
MIPI C-PHY TRx(80-2500Msps) / MIPI D-PHY TRx(80-4500Mbps) Combo PHY 5nm
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...
22
23.0
MIPI C-PHY TRx(80-2500Msps) / MIPI D-PHY TRx(80-4500Mbps) Combo PHY 5nm
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...
23
23.0
MIPI C-PHY TRx(80-8000Msps) / MIPI D-PHY TRx(80-9000Mbps) Combo PHY 4nm
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 9Gbps for D-PHY and 8Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Es...
24
20.0
MIPI C-PHY/D-PHY Combo(5nm, 7nm, 12/16nm, 28nm and 40nm)
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...
25
15.0
MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
The SVTPlus-CSI2-F is a second generation MIPI CSI2-Tx transmitter IP core for FPGA implementations. It complies with MIPI® CSI2 V2.0 and DPHY1.2 spec...
26
14.0
MIPI D-PHY for TSMC
D-PHY physical layer Developed by experienced teams with industry-leading domain expertise and extensively validated by multiple hardware platforms, ...
27
11.0
MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps
The MXL-CD-PHY-CSITX+-ST-28FDSOI is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificati...
28
11.0
MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 22ULP
The MXL-CDPHY-DSI-RX-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification f...
29
11.0
MIPI C-PHY/D-PHY Combo Universal IP, 4.5Gsps/4.5Gbps in TSMC 22ULP
The MXL-CD-PHY-UNIV-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification fo...
30
11.0
MIPI D-PHY
...
31
11.0
MIPI D-PHY IP 4.5Gbps in TSMC N7
The MXL-DPHY-DSI-TX-T-N07 is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for ...
32
11.0
MIPI D-PHY Universal IP in TSMC 28HPC+
The MXL-DPHY-UNIV-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificatio...
33
11.0
MIPI M-PHY HS-G4 IP (M-PHY v4.1) in TSMC 40G
The MXL-MIPI-M-PHY is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The IP can be used ...
34
10.0
D-phy 1.2 on tsmc 22nm with ultra low power
Arasan Chip Systems announces the immediate availability its MIPI D-PHY IP supporting speeds of upto 2.5 gbps for TSMC 22nm SoC designs. The MIPI D-...
35
10.0
MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 7 FF
Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes. Users are able to configure this Combo PHY into either D-PHY or C-PHY mode to supp...
36
10.0
MIPI D-PHY Receiver for TSMC 40nm LP
The Renesas MIPI D-PHY Receiver is useful 2 Data Channel receiver hard macro for CSI-2 of TSMC 40nm LP process....
37
10.0
MIPI D-PHY Transmitter/Receiver for DSI/CSI-2 Samsung 28nm FD-SOI
The Renesas MIPI D-PHY Transmitter/Receiver is useful 4 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of Samsung 28nm FD-SOI process....
38
10.0
MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP
The Renesas MIPI D-PHY Transmitter/Receiver is useful 2 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of TSMC 40nm LP process....
39
10.0
MIPI D-PHY TSMC 130nm
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
40
10.0
MIPI D-PHY TSMC 28nm HPC+ @ 2.5Ghz
The Arasan’s MIPI D-PHY Analog Transceiver IP Core is fully compliant to the D-PHY specification version 1.1. It supports the MIPI® Camera Serial Inte...
41
10.0
MIPI D-PHY Tx IP, Silicon Proven in TSMC 7FF
Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes. Users are able to configure this Combo PHY into either D-PHY or C-PHY mode to supp...
42
10.0
MIPI DSI-2 Transmitter Interface IP
MIPI DSI-2 (Display Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile dev...
43
10.0
MIPI M-PHY Designed For TSMC 28nm
ACS-AIP-MPHY-28HPM MIPI Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A...
44
10.0
MIPI M-PHY G4 Designed For TSMC 28nm HPC+
ACS-AIP-MPHY-28HPC+ MIPI Specification Version 4.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. ...
45
10.0
Automotive MIPI A-PHY Sink IP (2-Lane)
The CL12912IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS an...
46
10.0
Automotive MIPI A-PHY Source IP - 1-Lane
The CL12911IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS an...
47
7.0
MIPI C-PHY 8Gsps / D-PHY 9Gbps TRX Combo PHY (2nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 9Gbps for D-PHY and 8Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Es...
48
6.0
MIPI D-PHY Receiver with PPI
SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...
49
5.0
MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...
50
5.0
MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...