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71 IP
51
0.0
SPI Master IP
SmartDV's SPI Master IP is a silicon-proven, fully featured Serial Peripheral Interface master solution purpose-built for SoC designs requiring flexib...
52
0.0
SPI Slave IP
SmartDV's SPI Slave IP is a silicon-proven, fully featured Serial Peripheral Interface slave solution purpose-built for SoC designs requiring reliable...
53
0.0
SPI Slave to AHB Bridge IP
SmartDV's SPI Slave to AHB Bridge IP is a silicon-proven, fully featured serial peripheral interface bridge solution purpose-built for SoC designs req...
54
0.0
SPI Slave to AXI Bridge IP
SmartDV's SPI Slave to AXI Bridge IP is a silicon-proven, fully featured serial peripheral interface bridge solution purpose-built for SoC designs req...
55
0.0
MSC Microsecond Channel high-speed controller
The MSC-CTRL IP core implements a high-speed serial interface controller designed to connect a microcontroller or SoC to external power devices or sen...
56
0.0
eSPI Controller IP
SmartDV's eSPI Controller IP is a silicon-proven, fully featured Enhanced Serial Peripheral Interface controller solution purpose-built for SoC design...
57
0.0
xSPI Master IP
SmartDV's xSPI Master IP is a silicon-proven, fully featured eXtended Serial Peripheral Interface master solution purpose-built for SoC designs requir...
58
0.0
QSPI Master IP
SmartDV's QSPI Master IP is a silicon-proven, high-performance Quad SPI flash memory controller purpose-built for SoC designs requiring flexible, high...
59
0.0
eSPI Target IP
SmartDV's eSPI Target IP is a silicon-proven, fully featured Enhanced Serial Peripheral Interface target solution purpose-built for SoC designs requir...
60
0.0
eSPI Target to LPC Bridge IP
SmartDV's eSPI Target to LPC Bridge IP is a silicon-proven, fully featured protocol bridge solution purpose-built for SoC designs requiring seamless c...
61
0.0
HSSTP Link
The High-Speed Serial Trace Port (HSSTP) Controller IP implements the ARM HSSTP protocol. HSSTP replaces the existing parallel data output port, enab...
62
0.0
HSSTP PHY TX (5nm) (1.5 Gbps, 3 Gbps, and 6 Gbps) SF5A
The HSSTP TX PHY is a 5nm hard macro supporting up to 6Gbps data rates with dual lanes and a hybrid mode driver for AC-coupled links. It includes feat...
63
0.0
JTAG Master IP
SmartDV's JTAG Master IP is a silicon-proven, fully featured boundary scan controller engineered for SoC designs requiring reliable, standards-complia...
64
0.0
JTAG Slave IP
SmartDV's JTAG Slave IP is a silicon-proven, fully featured boundary scan solution engineered for SoC designs requiring reliable, standards-compliant ...
65
0.0
JTAG Slave To AHB Bridge IP
SmartDV's JTAG Slave to AHB Bridge IP is a silicon-proven, high-performance debug and test access solution engineered for SoC designs requiring seamle...
66
0.0
JTAG Slave To APB Bridge IP
SmartDV's JTAG Slave to APB Bridge IP is a silicon-proven, lightweight debug and test access solution engineered for SoC designs requiring seamless co...
67
0.0
JTAG Slave To AXI Bridge IP
SmartDV's JTAG Slave to AXI Bridge IP is a silicon-proven, high-performance debug and test access solution engineered for SoC designs requiring seamle...
68
0.0
AVSBus 1.x Master IP
SmartDV's AVSBus 1.x Master IP is a silicon-proven, fully featured Adaptive Voltage Scaling Bus master solution purpose-built for SoC, ASIC, and FPGA ...
69
0.0
AVSBus 1.x Slave IP
SmartDV's AVSBus 1.x Slave IP is a silicon-proven, fully featured Adaptive Voltage Scaling Bus slave solution purpose-built for Point of Load voltage ...
70
0.0
AVSBus 2.x Controller IP
SmartDV's AVSBus 2.x Master IP is a silicon-proven, fully featured Adaptive Voltage Scaling Bus master solution purpose-built for SoC, ASIC, and FPGA ...
71
0.0
AVSBus 2.x Target IP
SmartDV's AVSBus 2.x Slave IP is a silicon-proven, fully featured Adaptive Voltage Scaling Bus slave solution purpose-built for Point of Load voltage ...
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