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16 IP
1
14.0
Multi Standard programmable SERDES PHY with single/multi-lane configurations with support of long-reach channel
This 12.5Gbps SERDES IP is designed for smooth integration of Multiple SERDES lanes offering best in class performance, area and power. The programmab...
2
12.0
Serial ATA (SATA) I/II PHY IP CORE
SMS6000 is a Serial ATA gen I and gen II compliant PHY IP which supports SAPIS and Serial Attached SCCI (SAS) specifications both at 1.5 Gbp/s and 3.0...
3
5.0
SAS Initiator, 12G, 4 Ports, 48 Gbps, SATA Host
The SAS Initiator Controller IP Core provides an interface to high-speed serial link replacement for the parallel SCSI attachment of mass storage devi...
4
5.0
SATA/SAS 3.0 PHY
With sophisticated architecture and advanced technology, KNiulink SATA/SAS transceiver IP with PMA and PCS layer is designed for low power and high pe...
5
3.0
Multi-Link Multi-Protocol SerDes 16Gbps in TSMC 28HPC
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
6
1.0
10G Multi-SerDes PHY
The Innosilicon 10G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 10Gbps within a single lane. The PHY can be configured ...
7
1.0
12.5G Multi-SerDes PHY
The Innosilicon 12.5G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 12.5Gbps within a single lane. For this particular da...
8
1.0
32G Multi-SerDes For PCIe5.0/USB3.x PHY
The Innosilicon 32G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 32Gbps within a single lane. For this datasheet, the PH...
9
1.0
25G Multi-SerDes PHY
The Innosilicon 25G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datash...
10
0.118
SATA II PHY IP, Gen-2, 1 - port, UMC 0.18um G2 process
1.5G/3.0Gbps 1 port Serial ATA PHY and ESATA, UMC 0.18um GII Logic process....
11
0.118
SATA II PHY IP, Gen-2, UMC 0.11um HS/AE process
3G/1.5G Serial ATA PHY, UMC 0.11um HS/AE (AL Advance Enhancement) Logic process....
12
0.118
SATA II PHY IP, Gen-2, UMC 0.13um HS/FSG process
Serial ATA (SATA) physical layer that provides a complete range of host and device functions, UMC 0.13um HS/FSG Logic process....
13
0.118
SATA II PHY IP, Gen-2, UMC 0.13um HS/FSG process
Over sampling 1 port 3G/1.5G SATA PHY, UMC 0.13um HS+LL/FSG Logic process....
14
0.118
SATA II PHY IP, Gen-2, UMC 90nm SP process
Serial ATA I II PHY, UMC 90nm SP/RVT Low-K Logic process....
15
0.118
SATA II PHY IP, Support SATA Gen1 1.5Gb/s and SATA Gen2 3.0Gb/s, UMC 0.18um Logic process
Single channel serial ATA PHY layer compliant with SATA spec. of 3.0Gbps....
16
0.0
12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 12SF++
The multi-protocol SerDes PHY includes Peripheral Component Interconnect Express (PCIe) conforming with PCIe 2.0 Base Specification with support for P...
