Design & Reuse
13 IP
1
10.0
USB 3.0 SSPHY in GF (22nm)
The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer a...
2
6.0
USB 2.0 PHY; SMIC 40nm LL
...
3
6.0
USB 2.0 PHY; SMIC 55nm LL
...
4
1.0
IBM 65nm USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB anal...
5
1.0
GLOBALFOUNDARIES 22nm FDSOI USB3.0 Dual Role PHY/OTG PHY
This USB3.0 PHY IP is designed according to USB3.0 and USB2.0 specification. It supports the USB3.0 5Gbps Super-Speed mode and is backward compatible ...
6
1.0
SMIC 0.13um USB 1.1 PHY
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial Bus. It receives dat...
7
1.0
SMIC 0.13um USB 1.1 PHY
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial Bus. It receives dat...
8
1.0
SMIC 65nm USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB anal...
9
0.118
USB 3.0 OTG PHY IP, UMC 0.11um HS/AE process
USB3.0 PHY, UMC 0.11um HS/AE Logic process....
10
0.118
USB 3.0 OTG PHY IP, UMC 0.11um HS/FSG process
USB3.0 PHY, UMC 0.11um HS/FSG (Cu) Logic process....
11
0.118
USB 3.0 OTG PHY IP, UMC 0.13um HS/FSG process
USB3.0 OTG PHY, UMC 0.13um HS/FSG Logic process....
12
0.118
USB 3.0 OTG PHY IP, UMC 55nm SP process
USB3.0 PHY, UMC 55nm SP/RVT Low-K Logic process....
13
0.118
USB 3.0 OTG PHY IP, UMC 90nm SP process
USB 3.0 Transceiver, UMC 90nm SP/RVT Low-K Logic process....