Design & Reuse
20 IP
1
9.0
USB 2.0 Device, Software Enumeration FIFO Interface (USB20SF)
The USB 2.0 Device, Software Enumeration FIFO interface (USB20SF) IP Core is a FIFO based USB 2.0 device core with 32-bit Avalon/AXI interface and ULP...
2
9.0
USB 2.0 HUB (USB20HUB)
The USB 2.0 Hub IP core provides a link between the USB2.0 Host and multiple USB peripherals via UTMI + Low pin interface (ULPI). It supports High spe...
3
9.0
USB 2.0 On-The-Go (USB20OTG)
The USB 2.0 On-The-Go (OTG) IP Core is a 32-bit Avalon interface compliant core and supports ULPI interface. It supports both USB Host and USB Device ...
4
7.0
USB 2.0 Full/Low-Speed Device Core
The FHG USB DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-speed USB 2.0 device functionality wi...
5
7.0
USB 2.0 Full/Low-Speed Embedded Host Controller
The FHG USB EHC is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-/low-speed USB 2.0 host functionality ...
6
7.0
USB 2.0 High/Full-Speed Device Core
The FHG USB2 DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high-/full-speed USB 2.0 device functiona...
7
7.0
USB 2.0 High/Full/Low-Speed Embedded Host Controller
The FHG USB2 EHC is a scalable, high performance IP-module for usage in ASIC and FPGA designs to integrate high/full/low-speed USB 2.0 host functiona...
8
7.0
USB 2.0 OTG Full/Low-Speed Dual Role Core
The FHG USB OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-/low-speed USB 2.0 device and host ...
9
7.0
USB 2.0 OTG High/Full/Low-Speed Dual Role Core
The FHG USB2 OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high/full/low-speed USB 2.0 device and ...
10
1.0
USB 2.0 PHY TSMC 40LPeDRAM
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...
11
0.118
USB 1.1.OTG PHY IP, HJTC 0.18um eFlash/G2 process
HJTC 0.18um eFlash process, USB 1.1 OTG....
12
0.118
USB 1.1.OTG PHY IP, OTG, UMC 0.11um HS/AE process
USB1.1 PHY feature USB 1.1 On-The-Go PHY, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process....
13
0.118
USB 1.1.OTG PHY IP, UMC 0.13um HS/FSG process
0.13um OTG PHY, UMC 0.13um HS/FSG process....
14
0.118
USB 2.0 OTG PHY IP, UMC 0.13um HS/FSG process
USB 2.0 On-The-Go PHY, UMC 0.13um HS/FSG Logic process....
15
0.118
USB 2.0 OTG PHY IP, UMC 0.18um G2 process
USB 2.0 On-The-Go PHY, UMC 0.18um GII Logic RVT/FSG process....
16
0.118
USB 2.0 OTG PHY IP, UMC 0.25um process
USB 2.0 host On-The-Go PHY, UMC 0.25um Logic process....
17
0.118
USB 2.0 OTG PHY IP, UMC 40nm LP process
OTG USB2.0 UMC 40 nm LP/RVT process....
18
0.118
USB 2.0 OTG PHY IP, UMC 55nm eFlash process
USB2.0 OTG PHY, UMC 55nm eFlash process....
19
0.118
USB 2.0 OTG PHY IP, UMC 55nm LP process
USB2.0 OTG PHY (VDT and ID are included in PHY), UMC 55nm LP Low-K Logic process....
20
0.0
USB2 - DUSB2-ULPI - USB 2.0 Device Controller with ULPI interface
The DUSB2-ULPI is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver. The DUSB2-ULPI cont...