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61 IP
1
100.0
USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...
2
100.0
USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...
3
50.0
USB 2.0 nanoPHY in SMIC (65nm)
The Synopsys USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution, designed for low-power mobile and consumer applicati...
4
50.0
USB 2.0 PHY IP, Silicon Proven in TSMC 22ULP
The USB 2.0 PHY IP Core is a full physical layer (PHY) IP solution created for excellent performance and low power consumption. The High-Speed USB 2.0...
5
40.0
USB 2.0 PHY
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...
6
25.0
eUSB 2.0 PHY in TSMC (N5, N4P, N3E, N3P)
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
7
20.0
USB2.0 PHY, 8-bit or a 16-bit parallel interface, remaining backward compatible with USB1.1 legacy protocol at 12Mbps
KA13UGUSB20ST001 is USB2.0 physical layer transceiver (PHY) integrated circuits. The PHY can be configured for either an 8-bit or a 16-bit parallel in...
8
16.0
USB2.0 Host Transceiver PHY
USB 2.0 HOST Transceiver is a fully integrated PHY Core which is a super-set of HOST PHY with High Speed (HS), Full-Speed (FS) and Low-Speed Transceiv...
9
14.0
USB 2.0 PHY for TSMC
Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power The ubiquity of USB 2.0 in devices makes it nearly mandatory fo...
10
12.0
USB 2.0 Device Transceiver PHY
...
11
10.0
USB 2.0 femtoPHY in GF (28nm, 22nm, 12nm)
The Synopsys IP USB 2.0 femtoPHY provides designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer applications su...
12
10.0
USB 2.0 nanoPHY in GF (55nm)
The Synopsys USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution, designed for low-power mobile and consumer applicati...
13
10.0
USB 2.0 nanoPHY in UMC (65nm)
The Synopsys USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution, designed for low-power mobile and consumer applicati...
14
10.0
USB 2.0 picoPHY in GF (40nm, 28nm)
The Synopsys USB 2.0 picoPHY provides designers with a complete physical (PHY) layer IP solution, designed for low power mobile and consumer applicati...
15
5.0
M31 eUSB2 PHY IP(2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 28nm)
Embedded USB2 (eUSB2) is a new generation specification proposed by USB Association that extends USB 2.0 specification and uses 1.2V/1.0V as the inter...
16
1.0
SMIC 0.11um USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB anal...
17
1.0
USB 1.1 PHY
The USB1.1 PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB1.1 core with RCV, VM and VP. It is desig...
18
1.0
USB 1.1 PHY
The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed...
19
1.0
USB 1.1 PHY
The USB1.1 PHY is an IP version of USB transceiver. It receives data with DP and DM, and transfers data to USB1.1 core with RCV, VM and VP. It is desi...
20
1.0
USB 2.0 DRD Controller
Innosilicon USB2.0 DRD Controller provides a USB2.0-compliant host/device controller solution. This controller can be programmed to support data trans...
21
1.0
USB 3.0 DRD Controller
Innosilicon USB3.0 DRD Controller provides a USB3.0-compliant host/device controller solution. This controller can be programmed to support data trans...
22
1.0
USB HSIC PHY - High Speed Inter-Chip IP Core
USB is the ubiquitous peripherals interconnect of choice for large number of computing and consumer applications. Many systems provide a comprehensive...
23
1.0
USB1.1 PHY
The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed...
24
1.0
USB1.1 PHY
The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed...
25
1.0
USB1.1 PHY
The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed...
26
1.0
USB2.0 OTG PHY
The INNO USB 2.0 PHY conforms to the specification of UTMI+ level 3 Revision 1.0 (USB 2.0 Transceiver Macrocell Interface Plus) and has excellent perf...
27
1.0
USB3.1/3.0 PHY & Controller
The Innosilicon USB3.0 PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface fo...
28
1.0
USB3.2 PHY & Controller
INNOSILICON™ USB3.2 Controller and PHY IP is a highly customizable IP module that converts high-speed serial data into parallel data, and is compliant...
29
1.0
GSMC 0.18um USB 1.1 PHY
The USB1.1 PHY is an IP version of USB transceiver. It receives data via DP and DM, and transfers data to USB1.1 core via RCV, VM and VP. It is design...
30
1.0
TSMC 55nm USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB anal...
31
1.0
Type-C PHY
Innosilicon Type-C IP is composed of the physical layer and the PHY logic. The physical layer contains 4 data channels, an AUX channel and bias circui...
32
0.118
USB 1.1 PHY IP, UMC 0.13um HS/FSG process
USB 1.1 PHY, UMC 0.13um HS/FSG Logic process....
33
0.118
USB 1.1 PHY IP, UMC 0.15um SP process
USB 1.1 PHY, UMC 0.15um SP Logic process....
34
0.118
USB 1.1 PHY IP, UMC 0.18um eFlash/G2 process
USB 1.1 PHY, UMC 0.18um e-flash process....
35
0.118
USB 1.1 PHY IP, UMC 65nm SP process
ID Detector for USB OTG Function, UMC 65nm SP/HVT Low-K Logic process....
36
0.118
USB 2.0 Device PHY IP, UMC 0.11um HS/AE process
USB 2.0 PHY, UMC 0.11um HS/AE standard Logic process....
37
0.118
USB 2.0 Device PHY IP, UMC 0.11um HS/FSG process
USB 2.0 PHY, UMC 0.11um HS Logic process....
38
0.118
USB 2.0 Device PHY IP, UMC 0.11um LL/FSG process
USB 2.0 PHY, UMC 0.11um LL Logic process....
39
0.118
USB 2.0 Device PHY IP, UMC 0.13um CIS process
USB 2.0 PHY, UMC 0.13um CMOS Image Sensor process....
40
0.118
USB 2.0 Device PHY IP, UMC 0.18um CIS process
USB2.0 PHY, UMC 0.18um CMOS Image Sensor process....
41
0.118
USB 2.0 Device PHY IP, UMC 0.18um G2 process
USB2.0 PHY, UMC 0.18um GII Logic process....
42
0.0
USB 2.0 PHY for Samsung 7LPP
Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power The ubiquity of USB 2.0 in devices makes it nearly mandatory fo...
43
0.0
USB 2.0 PHY IP, Silicon Proven in SMIC 14SF+
The USB2.0 PHY IP is a comprehensive physical layer (PHY) IP solution created for exceptional performance and low power consumption. The High-Speed US...
44
0.0
USB 2.0 PHY IP, Silicon Proven in SMIC 40LL
The USB 2.0 PHY IP Core is a complete solution for the physical layer (PHY) that prioritizes both high performance and low power consumption. This ver...
45
0.0
USB 2.0 PHY IP, Silicon Proven in SMIC 55LL
The USB2.0 PHY IP is a comprehensive physical layer (PHY) IP solution created for exceptional performance and low power consumption. The High-Speed US...
46
0.0
USB 2.0 PHY IP, Silicon Proven in TSMC 12FFC
The whole physical layer (PHY) IP solution for USB 2.0 was designed for outstanding performance and low power consumption. The High-Speed USB 2.0 Tran...
47
0.0
USB 2.0 PHY IP, Silicon Proven in TSMC 16FFC
The entire physical layer (PHY) IP solution for USB 2.0 was created to provide exceptional performance and consume little power. The USB2.0 IP impleme...
48
0.0
USB 2.0 PHY IP, Silicon Proven in TSMC 28HPC+
The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption. For usage with either hosts, dev...
49
0.0
USB 2.0 PHY IP, Silicon Proven in TSMC 40LP/LL
The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption. For usage with either hosts, dev...
50
0.0
USB 2.0 PHY IP, Silicon Proven in TSMC 55LP
In order to deliver great performance and use little power, the whole physical layer (PHY) IP solution for USB 2.0 was developed. The High-Speed USB 2...
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