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78 IP
1
60.0
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devices, including graphic...
2
40.0
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP
This Display Port v1.4 Rx PHY IP Core supports Channel capacity, offering programmable analog characteristics like CDR Bandwidth, Equalizer Strength, ...
3
40.0
DP/eDP1.4b RX PHY
Silicon Library's eDP/DP1.4b RX PHY IP supports 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps, depending on the technology node. This silicon proven IP is a...
4
40.0
DP/eDP1.4b TX PHY
Silicon Library's eDP/DP1.4b TX PHY IP supports 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps, depending on the technology node. This silicon proven IP is a...
5
35.0
VESA VDC-M V1.2 Decoder
Embrace the future of digital media with Arasan's VESA VDC-M v1.2 Decoder. Our groundbreaking product revolutionizes video compression technology, off...
6
26.0
VESA Display Stream Compression (DSC) IP Core
Display Stream Compression offers inter-operable, visually lossless real-time, video compression to satisfy the emerging high bandwidth and high resol...
7
26.0
DisplayPort 1.4a IP Core
DisplayPort heralds a new alternative in video connectivity. Designed to enable low cost direct drive monitors and backed by industry leaders (Intel, ...
8
20.0
VESA VDC-M Decoder
The Video Electronics Standards Association (VESA®) introduced the VESA Display Compression-M (VDC-M) standard, a new display interface compression st...
9
20.0
DSC Decoder
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data compression and has b...
10
20.0
DSC Encoder
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data compression and has b...
11
15.0
DP/eDP1.4b RX Controller
Silicon Library’ｓeDP/DP1.4b RX Controller works with PHY IPs by Silicon Library or customers' PHYs....
12
15.0
DP/eDP1.4b TX Controller
Silicon Library’ｓeDP/DP1.4b TX Controller works with PHY IPs by Silicon Library or customers' PHYs....
13
10.0
VESA DSC Encoder and Decoder IP Solutions
Synopsys VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-high-definition displa...
14
8.0
Scalable Ultra-High Throughput DSC 1.2b Decoder
The UHT-DSC-D core is a scalable, ultra-high throughput, advanced DSC 1.2b decoder, compliant to the VESA Display Stream Compression (DSC) 1.2b standa...
15
8.0
Scalable Ultra-High Throughput DSC 1.2b Encoder
The UHT-DSC-E core is a scalable, ultra-high throughput, advanced DSC 1.2b encoder, compliant to the VESA Display Stream Compression (DSC) 1.2b standa...
16
7.0
DSC decoder IP
DSC decoder IP is compliant with standard VESA Display Stream Compression version 1.1/1.2/1.2a....
17
5.0
M31 DisplayPort RX IP in 6/7nm, 22nm
M31 DisplayPort RX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort RX supp...
18
5.0
DisplayPort TX IP for high-bandwidth applications (6nm, 12nm, 28nm)
M31 DisplayPort TX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort TX supp...
19
4.0
DisplayPort Transmitter & Receiver
Logic Fruit Technologies has designed & implemented DISPLAY PORT Transmitter & Receiver IP Cores supporting multiple line rates up to 8.1Gbps. The IP ...
20
2.0
DSC 1.2b Decoder
The DSC 1.2b Decoder is an efficient video decompression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for ...
21
2.0
DSC 1.2b Encoder
The DSC 1.2b Encoder is an efficient video compression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for lo...
22
1.0
eDP v1.5a RX PHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...
23
1.0
eDP v1.5a RX PHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...
24
1.0
eDP v1.5a RXPHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1 Gbps), and the general mode supports a maximum data rate of up to 4 Gbps. This core IP ...
25
1.0
DP 1.4 / eDP v1.4b TXPHY (14nm)
The eDP v1.4b TX PHY IP consists of a hard macro architecture supporting embedded DisplayPort v1.4 specification with data rates up to 8.1 Gbps per la...
26
1.0
DP 1.4 / eDP v1.4b TXPHY (4nm)
The eDP v1.4b TX PHY IP consists of a hard macro architecture supporting embedded DisplayPort v1.4 specification with data rates up to 8.1 Gbps per la...
27
1.0
DP 1.4 / eDP v1.4b TXPHY (8nm)
The eDP v1.4b TX PHY IP consists of a hard macro architecture supporting embedded DisplayPort v1.4 specification with data rates up to 8.1 Gbps per la...
28
1.0
DP 2.1a / eDP v1.5a RXPHY (4nm)
The DP/eDP RX PHY supports a maximum data rate of up to HBR3 (8.1 Gbps), and the general mode supports a maximum data rate of up to 4 Gbps. This core ...
29
1.0
DP/eDP1.4/1.2 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
30
1.0
DP/eDP1.4/1.2 TX PHY&controller
Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...
31
0.0
VDC-M (VESA Display Compression-M) Decoder
The Rambus VESA VDC-M 1.2 Decoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliv...
32
0.0
VDC-M (VESA Display Compression-M) Encoder
The Rambus VESA VDC-M 1.2 Encoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 encoder to deliv...
33
0.0
VDC-M Decoder IP
VDC-M DECODER core is compliant with standard VESA Display Stream Compression version 1.1/1.2. Through its compatibility, it provides a simple interfa...
34
0.0
VDC-M Encoder IP
VDC-M ENCODER core is compliant with standard VESA Display Stream Compression version 1.1/1.2. Through its compatibility, it provides a simple interfa...
35
0.0
eDisplay Port v1.4 Rx PHY IP in 40LL, Silicon Proven in SMIC 40LL
The eDisplay Port v1.4 Rx PHY IP Core caters to chips requiring high-bandwidth communication with minimal power consumption. It serves as a multi-giga...
36
0.0
eDisplay Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 22ULP
eDP/DP Tx PHY is designed for chips that perform eDP/DP data communication while operating at low power consumption. The main link is a multi-gigabit ...
37
0.0
eDisplayPort v1.4 Receiver Controller IP Core
This eDisplayPort 1.4 Rx Controller IP Core is a versatile and comprehensive solution designed for easy integration into any SoC or FPGA development. ...
38
0.0
eDisplayPort v1.4 Transmitter Controller IP Core
This eDisplayPort 1.4 Tx Controller IP Core integrates into any SoC or FPGA development, supporting the eDisplayPort 1.4b specification. It can be imp...
39
0.0
eDP Receiver IP
SmartDV’s eDP (Embedded DisplayPort) Receiver IP is a high-performance solution tailored for advanced display interfaces across mobile, automotive, an...
40
0.0
eDP Transmitter IP
SmartDV’s eDP (Embedded DisplayPort) Transmitter IP is a high-performance solution designed for next-generation display applications in mobile, automo...
41
0.0
eDP1.4 Transmitter PHY
Innosilicon eDP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. I...
42
0.0
VESA DSC (Display Stream Compression) 1.2b Video Decoder
...
43
0.0
VESA DSC (Display Stream Compression) 1.2b Video Encoder
...
44
0.0
VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs
...
45
0.0
VESA DSC 1.2b Encoder for Xilinx FPGAs
...
46
0.0
VESA DSC Decoder IP
DSC DECODER core is compliant with standard VESA Display Stream Compression version 1.1/1.2/1.2a. Through its compatibility, it provides a simple inte...
47
0.0
VESA DSC Encoder IP
DSC ENCODER core is compliant with standard VESA Display Stream Compression version 1.1/1.2/1.2a. Through its compatibility, it provides a simple inte...
48
0.0
VESA DSC V1.2 Decoder
Arasan’s VESA DSC v1.2 decoder IP core compresses high-definition streams in real time at resolutions ranging from 480 to 8K. The core supports 8, 10,...
49
0.0
VESA DSC V1.2 Encoder
The Arasan’s VESA DSC v1.2 Encoder IP core compresses high-definition streams in real time at resolutions ranging from 480 to 8K. The core supports 8,...
50
0.0
VESA VDC-M V1.2 Encoder
Embrace the future of digital media with Arasan's VESA VDC-M v1.2 Encoder. Our groundbreaking product revolutionizes video compression technology, off...