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74 IP
1
100.0
VDC-M (VESA Display Compression-M) Decoder
The Rambus VESA VDC-M 1.2 Decoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliv...
2
100.0
VDC-M (VESA Display Compression-M) Encoder
The Rambus VESA VDC-M 1.2 Encoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 encoder to deliv...
3
100.0
VESA DisplayPort 1.4 Forward Error Correction (FEC) Receiver
The DisplayPort Forward Error Correction (FEC) Receiver IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPo...
4
100.0
VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA Displa...
5
100.0
VESA DSC (Display Stream Compression) 1.2b Video Decoder
...
6
100.0
VESA DSC (Display Stream Compression) 1.2b Video Encoder
...
7
100.0
VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs
...
8
100.0
VESA DSC 1.2b Encoder for Xilinx FPGAs
...
9
100.0
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 12FFC
The DisplayPort v1.4 Tx PHY IP in 12FFC is a modernistic technology designed to be integrated into chip designs for various devices, including graphic...
10
100.0
ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
The VESA DSC 1.1 Encoder IP Core for automotive displays implements a fully compliant VESA DSC 1.1 encoder. It contains additional safety features to ...
11
40.0
DP/eDP1.4b RX PHY
Silicon Library's eDP/DP1.4b RX PHY IP supports 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps, depending on the technology node. This silicon proven IP is a...
12
40.0
DP/eDP1.4b TX PHY
Silicon Library's eDP/DP1.4b TX PHY IP supports 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps, depending on the technology node. This silicon proven IP is a...
13
35.0
VESA VDC-M V1.2 Decoder
Embrace the future of digital media with Arasan's VESA VDC-M v1.2 Decoder. Our groundbreaking product revolutionizes video compression technology, off...
14
26.0
VESA Display Stream Compression (DSC) IP Core
Display Stream Compression offers inter-operable, visually lossless real-time, video compression to satisfy the emerging high bandwidth and high resol...
15
26.0
DisplayPort 1.4a IP Core
DisplayPort heralds a new alternative in video connectivity. Designed to enable low cost direct drive monitors and backed by industry leaders (Intel, ...
16
23.0
Display Stream Compression (DSC 1.2) Decoder
The Trilinear Technologies Display Stream Compression (DSC) Decoder core offers realtime decompression of high-definition streams with resolutions fro...
17
23.0
Display Stream Compression (DSC 1.2) Encoder
The Trilinear Technologies Display Stream Compression (DSC) Encoder offers real-time compression of high-definition streams with resolutions up to 8K....
18
23.0
DisplayPort Receiver Link Controller
Our 5th generation DisplayPort Receiver Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link rate...
19
23.0
DisplayPort Transmitter Link Controller
Our 5th generation DisplayPort Transmitter Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link r...
20
23.0
MST Topology Management Stack
The Trilinear Technologies DisplayPort Multi-stream Transport (MST) Topology Management Software enables developers to accelerate software development...
21
20.0
VESA VDC-M Decoder
The Video Electronics Standards Association (VESA®) introduced the VESA Display Compression-M (VDC-M) standard, a new display interface compression st...
22
20.0
DSC Decoder
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data compression and has b...
23
20.0
DSC Encoder
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data compression and has b...
24
15.0
DP/eDP1.4b RX Controller
Silicon Library’ｓeDP/DP1.4b RX Controller works with PHY IPs by Silicon Library or customers' PHYs....
25
15.0
DP/eDP1.4b TX Controller
Silicon Library’ｓeDP/DP1.4b TX Controller works with PHY IPs by Silicon Library or customers' PHYs....
26
10.0
M31 DisplayPort RX IP in 6/7nm,12/16nm, 22nm
M31 DisplayPort RX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort RX supp...
27
10.0
VESA DSC Encoder and Decoder IP Solutions
Synopsys VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-high-definition displa...
28
10.0
DisplayPort TX IP for high-bandwidth applications (12nm, 16nm, 28nm)
M31 DisplayPort TX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort TX supp...
29
8.0
Scalable Ultra-High Throughput DSC 1.2b Decoder
The UHT-DSC-D core is a scalable, ultra-high throughput, advanced DSC 1.2b decoder, compliant to the VESA Display Stream Compression (DSC) 1.2b standa...
30
8.0
Scalable Ultra-High Throughput DSC 1.2b Encoder
The UHT-DSC-E core is a scalable, ultra-high throughput, advanced DSC 1.2b encoder, compliant to the VESA Display Stream Compression (DSC) 1.2b standa...
31
4.0
DisplayPort Transmitter & Receiver
Logic Fruit Technologies has designed & implemented DISPLAY PORT Transmitter & Receiver IP Cores supporting multiple line rates up to 8.1Gbps. The IP ...
32
3.0
eDP v1.5a RX PHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...
33
3.0
eDP v1.5a RX PHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...
34
1.0
eDP1.4 Transmitter PHY
Innosilicon eDP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. I...
35
1.0
DP/eDP1.4/1.2 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
36
1.0
DP/eDP1.4/1.2 TX PHY&controller
Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...
37
1.0
DP1.1 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
38
1.0
DP1.2 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
39
1.0
DP1.2 Transmitter PHY
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
40
1.0
DP1.2 Transmitter PHY_40nm
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
41
1.0
DP1.4 Receiver Controller
This document describes the low power Innosilicon DP 1.4 Receiver controller, which is fully compliant with DP 1.4 specification and eDP 1.4 standard....
42
1.0
DP1.4 TX PHY
Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...
43
0.0
VDC-M 1.2 Decoder
The BTREE VDC-M 1.2 Decoder IP Core fully complies with VESA VDC-M 1.2 (Display Compression). Its visually lossless compression performance is up to 5...
44
0.0
VDC-M 1.2 Encoder
The BTREE VDC-M 1.2 Encoder IP Core fully complies with VESA VDC-M 1.2(Display Compression). Its visually lossless compression performance is up to 5:...
45
0.0
VDC-M Decoder IP
VDC-M DECODER core is compliant with standard VESA Display Stream Compression version 1.1/1.2. Through its compatibility, it provides a simple interfa...
46
0.0
VDC-M Encoder IP
VDC-M ENCODER core is compliant with standard VESA Display Stream Compression version 1.1/1.2. Through its compatibility, it provides a simple interfa...
47
0.0
eDisplay Port v1.4 Rx PHY IP in 40LL, Silicon Proven in SMIC 40LL
The eDisplay Port v1.4 Rx PHY IP Core caters to chips requiring high-bandwidth communication with minimal power consumption. It serves as a multi-giga...
48
0.0
eDisplay Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 22ULP
eDP/DP Tx PHY is designed for chips that perform eDP/DP data communication while operating at low power consumption. The main link is a multi-gigabit ...
49
0.0
eDisplayPort v1.4 Receiver Controller IP Core
This eDisplayPort 1.4 Rx Controller IP Core is a versatile and comprehensive solution designed for easy integration into any SoC or FPGA development. ...
50
0.0
eDisplayPort v1.4 Transmitter Controller IP Core
This eDisplayPort 1.4 Tx Controller IP Core integrates into any SoC or FPGA development, supporting the eDisplayPort 1.4b specification. It can be imp...