Design & Reuse
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1877 IP
551
5.0
SAS Initiator, 12G, 4 Ports, 48 Gbps, SATA Host
The SAS Initiator Controller IP Core provides an interface to high-speed serial link replacement for the parallel SCSI attachment of mass storage devi...
552
5.0
SATA/SAS 3.0 PHY
With sophisticated architecture and advanced technology, KNiulink SATA/SAS transceiver IP with PMA and PCS layer is designed for low power and high pe...
553
5.0
Scalable Ultra-High Throughput DSC 1.2b Decoder
The UHT-DSC-D core is a scalable, ultra-high throughput, advanced DSC 1.2b decoder, compliant to the VESA Display Stream Compression (DSC) 1.2b standa...
554
5.0
Scalable Ultra-High Throughput DSC 1.2b Encoder
The UHT-DSC-E core is a scalable, ultra-high throughput, advanced DSC 1.2b encoder, compliant to the VESA Display Stream Compression (DSC) 1.2b standa...
555
5.0
PDM-to-PCM Conversion with AMBA Interface
The AR36T01 is a soft macro low-power digital microphone interface modulator IP. The IP converts stereo/mono 1-bit pulse-density modulated (PDM) bit s...
556
5.0
Advanced Encryption Standard Module
The CC-AES-APB is a synthesisable Verilog model of a Advanced Encryption Standard module. The AES core can be efficiently implemented on FPGA and ASIC...
557
5.0
General Purpose Input/Output Controller
The CC-GPIO-APB is a synthesisable Verilog model of a General Purpose Input/Output Controller. The GPIO core can be efficiently implemented on FPGA an...
558
5.0
General Purpose Input/Output Controller
The CC-GPIO-AXI is a synthesisable Verilog model of a General Purpose Input/Output Controller. The GPIO core can be efficiently implemented on FPGA an...
559
5.0
SerDes Hard Macro-IP in GlobalFoundries 22FDX
Low-power, flexible and robust Serializer-de-serializer IP built upon a proven ring-PLL based architecture, Support for multiple protocols, as well a...
560
5.0
Peripheral Direct Memory Access Controller
The CC-PDMA-APB-AHB is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on ...
561
5.0
Peripheral Direct Memory Access Controller
The CC-PDMA-AXI-AXI is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on ...
562
5.0
AHB Cache Controller Core
The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave AHB processor interface and a 32-bit master AHB interface to the...
563
5.0
MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...
564
5.0
MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices. To further improve thr...
565
5.0
MIPI Compliant D-PHY TSMC 65LP
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
566
5.0
MIPI CSI-2
The MIPI CSI-2 IP core is a highly scalable and silicon-agnostic implementation of the MIPI Camera Serial Interface 2 version 4.1 targeting ASIC and ...
567
5.0
MIPI I3C Basic Target
The I3C-T core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Target controller core suitable for any I3C bus topology & complia...
568
5.0
MIPI RFFE Master IP Core
The MIPI RFFE Master controller IP is a highly optimized and technology agnostic implementation of the MIPI RFFE v.3.1 standard targeting both ASIC an...
569
5.0
MIPI RFFE Slave IP Core
The MIPI RFFE Slave controller IP is a highly optimized and technology and PHY agnostic implementation of the MIPI RFFE v.3.1 standard targeting both ...
570
5.0
MIPI SPMI Controller or Target
The SPMI-CTRL core implements a highly featured, easy-to-use controller for the MIPI System Power Management Interface (MIPI-SPMI) bus. It supports th...
571
5.0
MIPI SPMI Target Controller
The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor s...
572
5.0
MIPI-I3C Combo Host and Target interface controller IP for Sensor and Peripheral connection
The MIPI I3C (Improved Inter Integrated circuit) is a two wire bidirectional Serial Bus for sensor communication. The MIPI I3C interface has been ...
573
5.0
MIPI-I3C Combo IP Host/Target HDR-DDR compliance with Spec v1.1.1
MIPI I3C(Improved Inter Integrated Circuit) is a two-wire bidirectional serial Bus for sensors communication. The MIPI I3C interface has been develope...
574
5.0
DisplayPort TX IP for high-bandwidth applications (6nm, 12nm, 28nm)
M31 DisplayPort TX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort TX supp...
575
5.0
SOF-Calibrated 48MHz USB Clock
CT20101 extracts a precise 48MHz clock frequency underlying a USB 1.1 data stream. The device implements a loop that controls the output frequency o...
576
5.0
Configurable System Tick Counter
The CC-SYSTICK-APB is a synthesisable Verilog model of a system tick timer counter controller. The SYSTICK core can be efficiently implemented on FPGA...
577
5.0
Configurable Timer Counter
The CC-TIMER-APB is a synthesisable Verilog model timer counter controller. The TIMER core can be efficiently implemented on FPGA and ASIC technologie...
578
5.0
Configurable Watchdog Timer
The CC-WDT-APB is a synthesisable Verilog model of a watchdog timer controller. The WDT core can be efficiently implemented on FPGA and ASIC technolog...
579
5.0
Low/Full Speed USB Billboard Controller
The CT25100 is a Full-Speed USB controller, which enumerates as Billboard Device. It integrates all necessary infrastructures, including the CT201...
580
5.0
Low/Full Speed USB Physical Layer
CT25201 is a complete and high integrated USB 2.0 low speed and full speed transceiver implementing the physical layer of a USB compliant device. ...
581
5.0
SPI Master / Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...
582
5.0
SPI Serial Peripheral Interface Master/Slave
The CC-SPI-APB is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller. The SPI core can be efficiently implemen...
583
5.0
SPI Slave Controller (SPI2APB, SPI2AXI, SPI2AHB Bus)
The Digital Blocks DB-SPI-S-AMBA-BRIDGE is a Serial Port Interface (SPI) Controller Verilog IP Core supporting SPI Slave Interface to APB Master Bus. ...
584
5.0
USB 2.0 Hub Controller
...
585
5.0
USB 2.0 On-chip oscillator, termination resistors, and DP/DM short circuit protection (0.18u)
The KA18USB20 consists of the digital and analog blocks of the USB Transceiver Macrocell (UTMI) specifications. This macrocell is certified and compli...
586
5.0
USB 2.0 PHY
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...
587
5.0
USB Power Delivery 3.1 Physical Layer
CT20602 is a complete USB Power Delivery 3.1 Physical Layer. It also implements that part of the USB Power Delivery 3.1 Protocol Layer which are def...
588
5.0
USB-C Interface
CT20601 is a complete USB Type-C Interface which includes optional VCONN and VBUS management features. It implements the dual-role port CC1/CC2 inte...
589
5.0
eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)
The Digital Blocks DB-eSPI-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI...
590
5.0
eUSB Repeater
CT20603 IP implements a dual-role capable eUSB2 repeater enabling an eUSB2 PHY in SOCs to support connections with USB2.0 compliant hosts and peripher...
591
4.7619
PCIe refclk buffer (14nm)
The output buffer to deliver a differential clock signal from inside chip to outside for PCIe interface...
592
4.7619
PCIe refclk buffer (8nm)
The output buffer to deliver a differential clock signal from inside chip to outside for PCIe interface...
593
4.7619
MIPI C-PHY 8Gsps / D-PHY 9Gbps TRX Combo PHY (SF2P)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 9Gbps for D-PHY and 8Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Es...
594
4.7619
HSSTP Link
The High-Speed Serial Trace Port (HSSTP) Controller IP implements the ARM HSSTP protocol. HSSTP replaces the existing parallel data output port, enab...
595
4.7619
HSSTP PHY TX (5nm) (1.5 Gbps, 3 Gbps, and 6 Gbps)
The HSSTP TX PHY is a 5nm hard macro supporting up to 6Gbps data rates with dual lanes and a hybrid mode driver for AC-coupled links. It includes feat...
596
4.0
I2C Master Controller
The ntI2C_M is an I2C-bus multi-master interface controller and provides a cost-effective solution for a wide range of applications that require a low...
597
4.0
SAS 1-to-1 Speed Bridge with Sandbox
The IntelliProp SAS Bridge with Sandbox (IPP-SS115A-BR) design provides SAS compliant connections to a SAS host and a SAS device. The host and device ...
598
4.0
SAS Initiator Core
The IntelliProp IPC-SS105A-HI SAS Initiator Core is an industry standard Serial-SCSI (SAS) initiator core that enables host designs to connect to high...
599
4.0
SAS Target Core
The IntelliProp IPC-SS107A-DT SAS Target Core is an industry standard Serial-SCSI (SAS) Core that enables device applications to connect to high throu...
600
4.0
SATA "Y" Bridge
The IntelliProp SATA "Y" Bridge design (IPP-SA111A-BR) provides SATA compliant connections per SATA-IO 3.3 and a standard SATA interface to access dri...