Design & Reuse
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arrow Multi-Protocol PHY (36)
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1891 IP
701
3.0
I2C Master Controller w/FIFO (APB Bus)
The Digital Blocks DB-I2C-M-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AP...
702
3.0
I2C Slave Controller - Low Power, Low Noise Config of User Registers
The DB-I2C-S-SCL-CLK is an I2C Slave Controller IP Core focused on low power, low noise ASIC / ASSP designs requiring the configuration & control of r...
703
3.0
I2C Slave Controller w/FIFO (APB or AHB or AHB-Lite or AXI-Lite Bus)
The Digital Blocks DB-I2C-S-APB / DB-I2C-S-AHB / DB-I2C-S-AXI / DB-I2C-S-AVLN Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC,NIOS II or othe...
704
3.0
I2C Slave with AHB Master Bridge (I2C2AHB)
The DB-I2C-S-AHB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & c...
705
3.0
I2C Slave with APB Master Bridge (I2C2APB)
The DB-I2C-S-APB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & c...
706
3.0
I2C Slave with AXI Master Bridge (I2C2AXI4)
The DB-I2C-S-AXI-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & c...
707
3.0
<4Gbps Low Power D2D Interface
Custom die-to-die interface in 12/16nm process technology. The I/O cells are defined as TX only, and RX only and have two modes of operation, standard...
708
3.0
PCIe 4.0 PHY (8nm)
The PCIe PHY IP consists of hardmacro PMA and softmacro PCS compliant to PCIe Base 4.0 specification. This IP offers a cost-effective and low-power so...
709
3.0
PCIe 4.0 PHY (8nm)
The PCIe PHY IP consists of hardmacro PMA and softmacro PCS compliant to PCIe Base 4.0 specification. This IP offers a cost-effective and low-power so...
710
3.0
PCIe refclk buffer (14nm)
The output buffer to deliver a differential clock signal from inside chip to outside for PCIe interface...
711
3.0
PCIe refclk buffer (8nm)
The output buffer to deliver a differential clock signal from inside chip to outside for PCIe interface...
712
3.0
2D Graphics Hardware Accelerator (AXI4 Bus)
The DB9200AXI4 2D Graphics Engine Verilog IP Core targets low VLSI footprint, high-performance hardware accelerated graphics applications. The DB92...
713
3.0
eDP v1.5a RX PHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...
714
3.0
eDP v1.5a RX PHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...
715
3.0
ChaCha20 stream cipher core
The eSi-CHACHA20 core is an easy to use CHACHA20 stream cipher hardware accelerator that is compliant with the IETF RFC7539 standard. ChaCha20, along...
716
3.0
Three-Speed Inline I/O Library with ODIO in TSMC 22nm
This silicon-proven, flip chip library in TSMC 22nm boasts three variants of GPIOs and one ODIO. All GPIO and ODIO cells have NS and EW orientation. A...
717
3.0
UHS-II PHY for SD4/SD5 TSMC 12nm FF
SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely ar...
718
3.0
UHS-II PHY for SD4/SD5 TSMC 16nm FF
SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely ar...
719
3.0
High Performance, Low Latency PCIe Gen5 PHY
Terminus Circuits offers best-in-class PHY IP for PCI Express Gen 5/4/3/2/1. The PHY is designed for low latency, low power, small form factor, high i...
720
3.0
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in GF 28SLP process
TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
721
3.0
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
722
3.0
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 55LP process
TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
723
3.0
Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 65GP process
TERMINUS CIRCUITS USB 3.1 GEN2 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
724
3.0
Single Lane and Quad Lane 16Gbps PCIe4.0 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS PCIe GEN4.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
725
3.0
Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in GF 28SLP process
TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol a...
726
3.0
Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
727
3.0
Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 55LP process
TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
728
3.0
Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 65GP process
TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
729
3.0
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in GF 28SLP process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
730
3.0
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
731
3.0
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 55LP process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
732
3.0
Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 65GP process
TERMINUS CIRCUITS USB 3.1 GEN1 PHY is high performance, low power, low latency Single & Quad-Lane PHY that supports USB protocol and its signalling ne...
733
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY in Samsung 28LPP process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
734
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in GF 28SLP process
TERMINUS-CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single &Quad-Lane PCI Express PHY that supports PCI Express protocol and...
735
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 28HPC process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
736
3.0
Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 65G process
TERMINUS CIRCUITS PCIe GEN3.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol an...
737
3.0
MIPI 4.1 M-PHY HS Gear 4
MIPI M-PHY HS Gear 4 IP is compliant with the MIPI serial communication protocol for use in mobile systems where performance, power, and efficiency ar...
738
3.0
MIPI C-PHY TRx 2.5Gsps) / D-PHY TRx 4.5Gbps Combo PHY (8nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...
739
3.0
MIPI C-PHY TRx 2.5Gsps) / D-PHY TRx 4.5Gbps Combo PHY (8nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...
740
3.0
MIPI D-PHY NEC 90nm
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
741
3.0
MIPI D-PHY TRx 2.1Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
742
3.0
MIPI D-PHY TRx 2.15Gbps (28nm)
The MIPI D-PHY IP supports data rates of up to 2.15Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provi...
743
3.0
MIPI D-PHY TRx 2.1Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
744
3.0
MIPI D-PHY TRx 2.1Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
745
3.0
MIPI D-PHY TRx 2.5Gbps (11nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
746
3.0
MIPI D-PHY TRx 2.5Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
747
3.0
MIPI D-PHY TRx 2.5Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
748
3.0
MIPI D-PHY TRx 2.5Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
749
3.0
MIPI D-PHY TRx 2.5Gbps (28nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
750
3.0
MIPI D-PHY TRx 4.5Gbps (8nm)
The MIPI D-PHY IP supports data rates of up to 4.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...