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1931 IP
751
1.0
Samsung 28nm FDSOI USB3.0 and PCIE2 combo PHY
The USB3.0 Super-Speed / PCI Express Combo PHY is a programmable IP that is compatible with the PHY Interface for PCI Express and USB3.0 Super-Speed A...
752
1.0
Samsung 28nm FDSOI USB3.0 Type-C PHY
...
753
1.0
SATA 2 HOST ON CYCLONE 5 GX
The LDS SATA 2 HOST_C5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a ALTERA Cyclone V GX FPGA. The...
754
1.0
SATA Device Controller on Altera Arria II GX
The LDS SATA DEVICE AR2GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The...
755
1.0
SATA Device on Stratix IV GX
The LDS SATA DEVICE STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA STRATIX IV GX FPGA. ...
756
1.0
SATA Device on Virtex 6
The LDS SATA DEVICE XV6 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The LDS SATA D...
757
1.0
SATA Host Controller
The LDS SATA HOST STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Startix IV GX FPGA. Th...
758
1.0
SATA HOST Controller on Cyclone IV GX
The LDS SATA HOST C4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Cyclone IV GX FPGA. The ...
759
1.0
SATA Host Controller on Spartan 6 LXT FPGA
The LDS SATA HOST SP6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Spartan 6 FPGA. The LDS SATA HOST SP6 IP is co...
760
1.0
SATA Host controller on Virtex 5 FXT
The LDS SATA HOST XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is com...
761
1.0
SATA Host Controller on Virtex 6 LXT
The LDS SATA HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The LDS SATA HOST XV6 IP is com...
762
1.0
SATA Host on Altera Arria II GX
The LDS SATA HOST AR2GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The L...
763
1.0
SATA HOST Synchronous IP
The LDS SATA HOST XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is com...
764
1.0
SATA III HOST Controller on Virtex 6
The LDS SATA 3 HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 speed grade 2 FPGA. The LDS SATA 3 ...
765
1.0
SATA RECORDER ON VIRTEX 6
The LDS SATA RECORDER XV6 IP is a complete recorder system IP. It can be configured according the recording performance required and the quantity of ...
766
1.0
SATA RECORDER ON VIRTEX 7 GTX
...
767
1.0
IBM 65nm USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB anal...
768
1.0
PCIe 2.0 End Point IP Core - PCIe with FIFO Interface
The Arasan PCI Express End Point is a high-speed, high-performance, and lowpowerIP core that is fully compliant to the PCI Express Specification 1.1 a...
769
1.0
PCIe 4.0 Controller
The Innosilicon Gen1/2/3/4 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It’s a high performance, hig...
770
1.0
PCIe 4.0 PHY
The Innosilicon PCIe4.0 PHY is a highly configurable PHY capable of supporting speeds up to 16Gbps within a single lane. For this particular datasheet...
771
1.0
PCIe 6.0, CXL3.0 PHY & Controller
INNOSILICON™ PCIe 6.0 and CXL 3.0 IP solutions combines a high-performance controller and PHY and is fully compliant with PCIe 6.0, CXL 3.0, and PIPE ...
772
1.0
HDMI1.4 Receiver PHY
Innosilicon HDMI RX IP is designed to receive and recover the video and audio data from an HDMI source device for display applications. Innosilicon H...
773
1.0
HDMI1.4 Transmitter IP
Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...
774
1.0
HDMI2.0 Receiver PHY
Innosilicon HDMI RX IP is designed to receive and recover the video and audio data from an HDMI source device for display applications. Innosilicon H...
775
1.0
HDMI2.0 Receiver PHY & Controller
Innosilicon HDMI RX IP is composed of the digital controller, the PHY logic and physical layer. The digital controller receives video, audio, synchron...
776
1.0
HDMI2.0 TX Controller
Innosilicon HDMI TX Controller is designed for transmitting video and audio data from a video source device to a display device, which is compatible w...
777
1.0
HDMI2.0 TX PHY
Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...
778
1.0
HDMI2.0/1.4 RX PHY & Controller
Innosilicon HDMI RX IP is designed to receive and recover the video and audio data from a HDMI source device for display applications, which is compat...
779
1.0
HDMI2.0/1.4 TX PHY & Controller
Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...
780
1.0
HDMI2.1 Transmitter PHY & Controller
Innosilicon HDMI TX IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with HDMI...
781
1.0
HDMI2.1 TX Controller
Innosilicon HDMI TX Controller is designed for transmitting video and audio data from a video source device to a display device, which is compatible w...
782
1.0
HDMI2.1 TX PHY
Innosilicon HDMI TX PHY IP is designed for transmitting video and audio data from a video source device to a display device, which is compatible with ...
783
1.0
eDP v1.5a RX PHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...
784
1.0
eDP v1.5a RX PHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...
785
1.0
eDP v1.5a RXPHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1 Gbps), and the general mode supports a maximum data rate of up to 4 Gbps. This core IP ...
786
1.0
Serdes - SMIC 55nm Eflash
...
787
1.0
Serial ATA Dual Host Controller
The LDS_SATA HOST DUAL XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST DUAL XV5...
788
1.0
Serial Controller Interface
Inicore’s iniSCI Slave is a synthesizable, flexible, and structured VHDL implementation of a Serial Controller Interface (SCI) that uses a two-wire bu...
789
1.0
UFS 2.1 Device Controller compatible with MIPI M-PHY 3.1 and UniPro 1.6
Arasan Chip Systems is a leading SoC IP provider of a complete suite of JEDEC UFS compliant IP solutions, which consist of IP cores, verification IP, ...
790
1.0
UFS 2.1 Host Controller compatible with M-PHY 3.1 and UniPro 1.6
Arasan's Universal Flash Storage 2.1 (UFS 2.1) is a simple but high performance, serial interface primarily used in mobile systems, between host proce...
791
1.0
UFS 3.0 Host Controller compatible with M-PHY 4.0 and UniPro 1.8
Arasan's Universal Flash Storage 3.0 (UFS 3.0) is a simple but high performance, serial interface primarily used in mobile systems, between host proce...
792
1.0
UFS Host 2.1 Prototyping Kit (HDK )Total IP in a Box
Universal Flash Storage (UFS) is a simple, high performance, mass storage device with a serial line interface. UFS is designed to be the most advanced...
793
1.0
UFS Host 3.0 Prototyping Kit (HDK )Total IP in a Box
Universal Flash Storage (UFS) is a simple, high performance, mass storage device with a serial line interface. UFS is designed to be the most advanced...
794
1.0
5G Multi-SerDes For PCIe2.0/USB3.0 PHY
The Innosilicon 5Gbps SERDES PHY is a highly configurable PHY capable of supporting speeds up to 5Gbps within a single lane. For this datasheet, the P...
795
1.0
8G Multi-SerDes For PCIe3.0/USB3.0 PHY
The Innosilicon 8Gbps SERDES PHY is a highly configurable PHY capable of supporting speeds up to 8Gbps within a single lane. For this datasheet, the P...
796
1.0
Digital Down Converter core
The eSi-DDC is a Digital Down Converter combining a Digital Frequency Synthesizer (DDS) with a Digital Mixer. The DDS is implemented in a resource ef...
797
1.0
MIPI CSI2 Receiver Interface
The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile...
798
1.0
MIPI D-PHY TRx 2.15Gbps (28nm)
The MIPI D-PHY IP supports data rates of up to 2.15Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provi...
799
1.0
MIPI D-PHY TRx 2.1Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
800
1.0
MIPI D-PHY TX/CSI2 Link Controller
CD12631S4TIP is a link IP that allows you to link a camera module or CMOS image sensor (CIS) to a host system. This LINK IP is a soft macro IP that h...