Design & Reuse
arrow AMBA AHB / APB/ AXI (198)
arrow CXL (18)
arrow D2D (58)
arrow Gen-Z (6)
arrow HDMI (82)
arrow I2C (119)
arrow Interlaken (3)
arrow MIL-STD-1553 (3)
arrow MIPI (458)
arrow Multi-Protocol PHY (36)
arrow PCI (248)
arrow RapidIO (6)
arrow SAS (6)
arrow SATA (95)
arrow Smart Card (6)
arrow USB (388)
arrow V-by-One (22)
arrow VESA (74)
arrow Other (65)
1891 IP
951
1.0
SMIC 0.13um 1.2V/3.3V PCI I/O Cells Library
VeriSilicon SMIC 0.13um 1.2V/3.3V PCI I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation...
952
1.0
SMIC 0.13um USB 1.1 PHY
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial Bus. It receives dat...
953
1.0
SMIC 0.13um USB 1.1 PHY
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial Bus. It receives dat...
954
1.0
SMIC 0.18um PCI I/O Cells DUP Library
VeriSilicon SMIC 0.18um 1.8V/3.3V PCI I/O Cells Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporatio...
955
1.0
SMIC 0.18um PCI I/O Cells Library
VeriSilicon SMIC 0.18um 1.8V/3.3V PCI I/O Cells Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporatio...
956
1.0
SMIC 0.18um PCI-X IO
The PCI-X transceiver is a IP version of PCI-X I/O pads, which is fully compatible with PCI-X R1.0 specification....
957
1.0
SMIC 0.25um 2.5V/3.3V PCI I/O Cells Library
VeriSilicon SMIC 0.25um 2.5V/3.3V PCI I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation...
958
1.0
SMIC 110nm MIPI DPHY
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes. It can support both...
959
1.0
SMIC 28nm USB3.0 Dual Role PHY/Type-C
The USB3.0 Type-C PHY IP is designed to the USB 3.0, USB2.0 Specification and the USB Type-CTM USB Cable and Connector Specification Revision 1.1....
960
1.0
SMIC 55nm LL MIPI DPHY
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.1”, which consists of Bi-directional 1-Clock and 4-Data lanes. It can support both...
961
1.0
SMIC 55nm LL USB2.0 PHY
...
962
1.0
SMIC 55nm sub-LVDS Receiver
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors. The receiver consists of PHY only....
963
1.0
SMIC 55nm sub-LVDS Receiver
The sub-LVDS Receiver IP is designed as an interface to bridge Video Image Sensors and processors. The receiver consists of PHY only....
964
1.0
SMIC 65nm USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB anal...
965
1.0
Normal USB1.1 device PHY
...
966
1.0
Normal USB1.1 device PHY
...
967
1.0
Normal USB1.1 device PHY
...
968
1.0
DP/eDP1.4/1.2 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
969
1.0
DP/eDP1.4/1.2 TX PHY&controller
Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...
970
1.0
DP1.1 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
971
1.0
DP1.2 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
972
1.0
DP1.2 Transmitter PHY
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
973
1.0
DP1.2 Transmitter PHY_40nm
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
974
1.0
DP1.4 Receiver Controller
This document describes the low power Innosilicon DP 1.4 Receiver controller, which is fully compliant with DP 1.4 specification and eDP 1.4 standard....
975
1.0
DP1.4 TX PHY
Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...
976
1.0
Crystal-free USB1.1 device PHY
...
977
1.0
Crystal-less USB 1.1 Transceiver PHY
...
978
1.0
Crystal-less USB1.1 device PHY
...
979
1.0
Crystal-less USB1.1 device PHY total solution
...
980
1.0
Crystal-less USB1.1 device PHY total solution(XRG013EFDUSB2PY_DNXC50A)
Ultral-small size: 0.033mm2; High performance, low EMI TX driver design...
981
1.0
Crystal-less USB1.1 device PHY(No analog PADs)
...
982
1.0
Crystal-less USB2.0 device PHY
...
983
1.0
Crystal-less USB2.0 device PHY
...
984
1.0
Crystal-less USB2.0 device PHY
...
985
1.0
Crystal-less USB2.0 device PHY
...
986
1.0
crystalless USB1.1 PHY
The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial Bus. It receives dat...
987
1.0
RSA public key cryptography with APB interface
The standard RSA module is available as an APB peripheral, where it seamlessly integrates with EnSilica's cryptography library. The peripheral can be...
988
1.0
USB 1.1 PHY
The USB1.1 PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB1.1 core with RCV, VM and VP. It is desig...
989
1.0
USB 1.1 PHY
The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed...
990
1.0
USB 1.1 PHY
The USB1.1 PHY is an IP version of USB transceiver. It receives data with DP and DM, and transfers data to USB1.1 core with RCV, VM and VP. It is desi...
991
1.0
USB 2.0 Device Controller
The USB 2.0 Device IP core is Arasan’s latest development that enables designers in the PC, mobile, consumer and communication markets to bring signif...
992
1.0
USB 2.0 Device IP Core
A USB 2.0 Device IP Core that provides high performance small footprint solution for quick and easy implementation of a USB Device interface. The USB...
993
1.0
USB 2.0 DRD Controller
Innosilicon USB2.0 DRD Controller provides a USB2.0-compliant host/device controller solution. This controller can be programmed to support data trans...
994
1.0
USB 2.0 EHCI Host Controller IP
The Arasan USB 2.0 Host IP is an USB 2.0 specification compliant host IP core with an optional AHB, PCI, or custom host interface. The USB 2.0 Host IP...
995
1.0
USB 2.0 Hub Controller
The Arasan USB 2.0 Hub IP core is an USB 2.0 specification compliant hub core that supports 480 Mbit/s in High Speed (HS) mode, 12 Mbit/s in Full Spe...
996
1.0
USB 2.0 On-The-Go Controller
The Arasan USB 2.0 OTG IP Core is compliant with the OTG Supplement Rev. 1.0a. The USB 2.0 OTG core supports both Host Controller, Device Controller a...
997
1.0
USB 2.0 OTG Controller - SMIC 55nm Eflash
...
998
1.0
USB 2.0 PHY - SMIC 55nm Eflash
...
999
1.0
USB 2.0 PHY - SMIC 55nm Eflash
...
1000
1.0
USB 2.0 PHY For On-The-Go Controller
The Arasan ACS-AIP-USB2 USB 2.0 PHY IP core is a Transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specific...