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1940 IP
1051
0.118
USB 3.0 OTG PHY IP, UMC 0.11um HS/FSG process
USB3.0 PHY, UMC 0.11um HS/FSG (Cu) Logic process....
1052
0.118
USB 3.0 OTG PHY IP, UMC 0.13um HS/FSG process
USB3.0 OTG PHY, UMC 0.13um HS/FSG Logic process....
1053
0.118
USB 3.0 OTG PHY IP, UMC 40nm LP process
USB 3.0 PHY, UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT process....
1054
0.118
USB 3.0 OTG PHY IP, UMC 55nm SP process
USB3.0 PHY, UMC 55nm SP/RVT Low-K Logic process....
1055
0.118
USB 3.0 OTG PHY IP, UMC 90nm SP process
USB 3.0 Transceiver, UMC 90nm SP/RVT Low-K Logic process....
1056
0.118
USB 3.0 PHY; UMC 28nm HPC_Plus +RVT+LVT Logic Process
USB 3.0 PHY; UMC 28nm HPC_Plus +RVT+LVT Logic Process...
1057
0.118
USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process
USB 3.1 Gen.1 TYPE-C PHY ; UMC 40nm Logic/Mixed-Mode Low Power/RVT+LVT Process...
1058
0.118
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process, without internal power clamping circuit
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process, without internal power clamping circuit...
1059
0.118
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic e-Flash Process
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic e-Flash Process...
1060
0.118
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process
USB1.1 PHY Feature USB 1.1 On-The-Go PHY; UMC 55nm Logic Low Power Low-K Process...
1061
0.118
USB2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process_x005F_x005F_x005F_x005F_x005F_x000D_ cost down from FZOTG266HJ0C_A
USB2.0 On-The-Go PHY; UMC 28nm HPC RVT Logic Process cost down from FZOTG266HJ0C_A...
1062
0.118
USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF
USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF...
1063
0.118
USB3.0 OTG controller with AXI interface, support Host, Peripheral and OTG function
USB3.0 OTG controller with AXI interface, support Host, Peripheral and OTG function...
1064
0.118
FTVBOTXALL010 is a V-by-One transmitter designed for applications that take ultra-low power dissipation and high data transfer rate. This IP is compliant with the V-By-One HS Standard, Ver. 1.3. It transfers the packed packet from direct the video stream
FTVBOTXALL010 is a V-by-One transmitter designed for applications that take ultra-low power dissipation and high data transfer rate. This IP is compli...
1065
0.118
Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process.
Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process....
1066
0.118
AXI Bus Controller IP, Bus Controller, Soft IP
Register Slice Controller with AXI bus interface....
1067
0.118
AXI system Peripheral IP, AXI Bus System Interconnect, Soft IP
AXI bus interconnect....
1068
0.118
AXI system Peripheral IP, AXI to AXI Bridge, Soft IP
AMBA AXI to AXI Bridge....
1069
0.118
AXI system Peripheral IP, AXI/APB host bridge, Soft IP
AXI/APB host bridge controller....
1070
0.118
AXI system Peripheral IP, Cache Controller, L2 Cache, Soft IP
L2 cache controller with AXI interface....
1071
0.118
AXI system Peripheral IP, DMA controller for AXI master port and slave port (32 - bit, 64 - bit and 128 - bit), 8 channels DMA, Soft IP
DMA controller with AXI interface....
1072
0.118
AXI system Peripheral IP, Interrupt Controller, Soft IP
Generic Interrupt Controller with AXI interface. Faraday's FTINTC030 Generic interrupt controller supports software generated interrupt, private perip...
1073
0.0
A standard‑compliant I2S‑to‑AHB bridge
A standard‑compliant I2S‑to‑AHB bridge that seamlessly connects digital audio streams to system memory and processors while fully adhering to AMBA® 4 ...
1074
0.0
A standard‑compliant parallel‑to‑AHB bridge
A standard‑compliant parallel‑to‑AHB bridge that efficiently transfers parallel data streams into the system bus while fully adhering to AMBA® 4 speci...
1075
0.0
1-56G-PCIe Gen5 ePHY Multi-Protocol SerDes IP - 7nm Low Power and Latency
Ultra-high speed SerDes IP, adopted by global Tier-1 network/storage/5G OEMs and major semiconductor companies. eTopus is the pioneer on PAN4 ADC/DSP...
1076
0.0
V-By-One PHY & Controller (Tx+ Rx)
INNOSILICON™ VBO IP is designed for transmitting or receiving video signals between a video source device and display device, The IP is fully complian...
1077
0.0
V-By-One Receiver IP
VBYONE Receiver core is compliant with standard VByOne specification as 1.2/1.3/1.4. Through its compatibility, it provides a simple interface to a wi...
1078
0.0
V-By-One Receiver_8ch
Innosilicon VBO RX IP is designed to receive and recover the video data from a VBO source device for display applications. Innosilicon VBO RX IP is c...
1079
0.0
V-by-One Rx IP, Silicon Proven in 40G
Using internal equipment connections, the V-by-One HS technology seeks to send video signals at a high data rate. The V-by-One HS Standard outlines th...
1080
0.0
V-by-One Rx IP, Silicon Proven in SMIC 40LL
The V-by-One HS technology aims to transmit video signals at a high data rate using internal equipment connections. The requirements to create a trans...
1081
0.0
V-By-One Transmitter IP
VBYONE Transmitter core is compliant with standard VByOne specification as 1.2/1.3/1.4. Through its compatibility, it provides a simple interface to a...
1082
0.0
V-by-One Tx IP, Silicon Proven in 40G
The V-by-One HS technology aims to transmit video signals at a high data rate using an internal connection between devices. The requirements to create...
1083
0.0
V-by-One/ LVDS Tx IP, Silicon Proven in SMIC 40LL
The V-by-One® HS technology aims to transmit video signals at a high data rate using internal equipment connections. The requirements to create a tran...
1084
0.0
V-by-One/LVDS Rx IP, Silicon Proven in GF 22FDX
The V-by-One® HS technology aims to transmit video signals at a high data rate using internal equipment connections. The requirements to create a tran...
1085
0.0
V-by-One/LVDS Rx IP, Silicon Proven in SMIC 40LL
V-by-One® HS technology targets a high-speed data transmission of video signals based on internal connection of equipment. V-by-One® HS Standard defin...
1086
0.0
V-by-One/LVDS Tx Combo PHY, Silicon Proven in 28HPC+
V-by-One/ LVDS Tx Combo PHY IP Core aims at achieving high-speed data transmission for video signals through internal equipment connections. The V-by-...
1087
0.0
V-by-One/LVDS Tx IP, Silicon Proven in GF 22FDX
Based on internal equipment connections, the V-by-One® HS technology aims to transmit video signals at high data rates. The requirements to build a tr...
1088
0.0
6.25G SerDes in 55nm
The Actt's 6.25G SerDes IP is a 4-Channel Serdes configuration with 1 PLL, 4 TX channels and 4 RX channels. It’s based on SMIC 55nm embedded-flash tec...
1089
0.0
2.5G MIPI D-PHY in HLMC 28nm
The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specifi...
1090
0.0
1.5G MIPI D-PHY in SMIC 130nm~28nm
The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specifi...
1091
0.0
2.5G MIPI D-PHY in TSMC 22nm
The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specifi...
1092
0.0
2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Receiver
The SVRPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps. The highly parallel architecture ...
1093
0.0
2.5Gbps Per Lane MIPI-CSI2 Compliant Serial Video Transmitter
The SVTPlus supports a clock lane and 4 data lanes, each lane featuring at up to 2.5Gbps, for a total of 10Gbps. The highly parallel architecture of t...
1094
0.0
4.5Gbps/lane MIPI D-PHY in SMIC 28HKC+
BriteSemi’s MIPI D-PHY supports speed up to 4.5Gbps per lane and an aggregate data rate of 18Gbps, which can provide high-performance MIPI D-PHY solut...
1095
0.0
2.5Gbps/lane MIPI D-PHY in SMIC 40NLL
BriteSemi’s MIPI D-PHY supports speed up to 4.5Gbps per lane and an aggregate data rate of 18Gbps, which can provide high-performance MIPI D-PHY solut...
1096
0.0
10/100 Mbit Ethernet MAC
The GRETH core implements 10/100 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface. The core implements the 802.3-2002 Ethernet s...
1097
0.0
30G MR Multi-Protocol SerDes (MPS) PHY
Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging designs. The 30G...
1098
0.0
10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
Silicon-proven PHY for PCIe, USB, Ethernet, DisplayPort, and other protocols The Cadence® 10Gbps Multi-Link and Multi-Protocol PHY IP provides a fl...
1099
0.0
112G Multi-Rate SerDes
Empowering customers to thrive in the AI era, INNOSILICON™ introduces its most advanced 112G SerDes (Serializer/Deserializer) and Controller IP, purpo...
1100
0.0
112G PHY in TSMC (N7, N5)
Synopsys IP Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high perfor...
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