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1899 IP
1101
0.118
USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF
USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF...
1102
0.118
USB3.0 OTG controller with AXI interface, support Host, Peripheral and OTG function
USB3.0 OTG controller with AXI interface, support Host, Peripheral and OTG function...
1103
0.118
FTVBOTXALL010 is a V-by-One transmitter designed for applications that take ultra-low power dissipation and high data transfer rate. This IP is compliant with the V-By-One HS Standard, Ver. 1.3. It transfers the packed packet from direct the video stream
FTVBOTXALL010 is a V-by-One transmitter designed for applications that take ultra-low power dissipation and high data transfer rate. This IP is compli...
1104
0.118
Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process.
Two Port OTG USB2.0 PHY;BOAC version; Wire bonding;UMC 40 nm LP/RVT process....
1105
0.118
AXI Bus Controller IP, Bus Controller, Soft IP
Register Slice Controller with AXI bus interface....
1106
0.118
AXI system Peripheral IP, AXI Bus System Interconnect, Soft IP
AXI bus interconnect....
1107
0.118
AXI system Peripheral IP, AXI to AXI Bridge, Soft IP
AMBA AXI to AXI Bridge....
1108
0.118
AXI system Peripheral IP, AXI/APB host bridge, Soft IP
AXI/APB host bridge controller....
1109
0.118
AXI system Peripheral IP, Cache Controller, L2 Cache, Soft IP
L2 cache controller with AXI interface....
1110
0.118
AXI system Peripheral IP, DMA controller for AXI master port and slave port (32 - bit, 64 - bit and 128 - bit), 8 channels DMA, Soft IP
DMA controller with AXI interface....
1111
0.118
AXI system Peripheral IP, Interrupt Controller, Soft IP
Generic Interrupt Controller with AXI interface. Faraday's FTINTC030 Generic interrupt controller supports software generated interrupt, private perip...
1112
0.0
1-56G-PCIe Gen5 ePHY Multi-Protocol SerDes IP - 7nm Low Power and Latency
Ultra-high speed SerDes IP, adopted by global Tier-1 network/storage/5G OEMs and major semiconductor companies. eTopus is the pioneer on PAN4 ADC/DSP...
1113
0.0
V-By-One PHY & Controller (Tx+ Rx)
INNOSILICON™ VBO IP is designed for transmitting or receiving video signals between a video source device and display device, The IP is fully complian...
1114
0.0
V-By-One Receiver IP
VBYONE Receiver core is compliant with standard VByOne specification as 1.2/1.3/1.4. Through its compatibility, it provides a simple interface to a wi...
1115
0.0
V-By-One Receiver_8ch
Innosilicon VBO RX IP is designed to receive and recover the video data from a VBO source device for display applications. Innosilicon VBO RX IP is c...
1116
0.0
V-by-One Rx IP, Silicon Proven in 40G
Using internal equipment connections, the V-by-One HS technology seeks to send video signals at a high data rate. The V-by-One HS Standard outlines th...
1117
0.0
V-by-One Rx IP, Silicon Proven in SMIC 40LL
The V-by-One HS technology aims to transmit video signals at a high data rate using internal equipment connections. The requirements to create a trans...
1118
0.0
V-By-One Transmitter IP
VBYONE Transmitter core is compliant with standard VByOne specification as 1.2/1.3/1.4. Through its compatibility, it provides a simple interface to a...
1119
0.0
V-by-One Tx IP, Silicon Proven in 40G
The V-by-One HS technology aims to transmit video signals at a high data rate using an internal connection between devices. The requirements to create...
1120
0.0
V-by-One/ LVDS Tx IP, Silicon Proven in SMIC 40LL
The V-by-One® HS technology aims to transmit video signals at a high data rate using internal equipment connections. The requirements to create a tran...
1121
0.0
V-by-One/LVDS Rx IP, Silicon Proven in GF 22FDX
The V-by-One® HS technology aims to transmit video signals at a high data rate using internal equipment connections. The requirements to create a tran...
1122
0.0
V-by-One/LVDS Rx IP, Silicon Proven in SMIC 40LL
V-by-One® HS technology targets a high-speed data transmission of video signals based on internal connection of equipment. V-by-One® HS Standard defin...
1123
0.0
V-by-One/LVDS Tx Combo PHY, Silicon Proven in 28HPC+
V-by-One/ LVDS Tx Combo PHY IP Core aims at achieving high-speed data transmission for video signals through internal equipment connections. The V-by-...
1124
0.0
V-by-One/LVDS Tx IP, Silicon Proven in GF 22FDX
Based on internal equipment connections, the V-by-One® HS technology aims to transmit video signals at high data rates. The requirements to build a tr...
1125
0.0
6.25G SerDes in 55nm
The Actt's 6.25G SerDes IP is a 4-Channel Serdes configuration with 1 PLL, 4 TX channels and 4 RX channels. It’s based on SMIC 55nm embedded-flash tec...
1126
0.0
2.5G MIPI D-PHY in HLMC 28nm
The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specifi...
1127
0.0
1.5G MIPI D-PHY in SMIC 130nm~28nm
The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specifi...
1128
0.0
2.5G MIPI D-PHY in TSMC 22nm
The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specifi...
1129
0.0
4.5Gbps/lane MIPI D-PHY in SMIC 28HKC+
BriteSemi’s MIPI D-PHY supports speed up to 4.5Gbps per lane and an aggregate data rate of 18Gbps, which can provide high-performance MIPI D-PHY solut...
1130
0.0
2.5Gbps/lane MIPI D-PHY in SMIC 40NLL
BriteSemi’s MIPI D-PHY supports speed up to 4.5Gbps per lane and an aggregate data rate of 18Gbps, which can provide high-performance MIPI D-PHY solut...
1131
0.0
30G MR Multi-Protocol SerDes (MPS) PHY
Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challengings applications The ...
1132
0.0
40G Ultralink D2D PHY for TSMC N3P
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
1133
0.0
40G Ultralink D2D PHY for TSMC N5P
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
1134
0.0
40G Ultralink D2D PHY for TSMC N6, N7
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
1135
0.0
112G PHY in TSMC (N7, N5)
Synopsys IP Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high perfor...
1136
0.0
112G SerDes IP Core in 6nm
The 112G SerDes PHY IP Core in 6nm offers best-in-class serial link performance for advanced SoC designs. Supporting multi-rate operation from 1 Gbps ...
1137
0.0
112G SerDes PHY IP in 12nm
The 112G SerDes PHY IP Core, fabricated in 12nm FinFET technology, delivers scalable high-speed connectivity for modern SoC platforms. Supporting up t...
1138
0.0
112G Serdes PHY IP in 5nm
The 112 Gbps SerDes PHY IP Core, natively developed in 5 nm FinFET, unlocks unmatched serial speeds for SoC interconnects, supporting both PAM4 (56–11...
1139
0.0
112G VSR PHY in TSMC (N5, N3P)
Synopsys IP Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high perfor...
1140
0.0
112G-ULR PAM4 SerDes PHY for Samsung SF5A
112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...
1141
0.0
112G-ULR PAM4 SerDes PHY for TSMC N3E/N3P
112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...
1142
0.0
112G-ULR PAM4 SerDes PHY for TSMC N5/N4P
112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...
1143
0.0
112G-ULR PAM4 SerDes PHY for TSMC N6/N7
112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...
1144
0.0
112G-VSR for TSMC N3E/N3P
112G-VSR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...
1145
0.0
112Gbps VSR to extended LR SerDes IP on TSMC 16/12nm
Credo is a world leading SerDes Technology Company offers silicon proven SerDes IP from 1G to 100G data rates offering superior performance and power....
1146
0.0
112Gbps VSR to extended LR SerDes IP on TSMC N3
Credo is a world leading SerDes Technology Company offers silicon proven SerDes IP from 1G to 100G data rates offering superior performance and power....
1147
0.0
112Gbps VSR to extended LR SerDes IP on TSMC N5/N4
Credo is a world leading SerDes Technology Company offers silicon proven SerDes IP from 1G to 100G data rates offering superior performance and power....
1148
0.0
112Gbps VSR to extended LR SerDes IP on TSMC N7/N6
Credo is a world leading SerDes Technology Company offers silicon proven SerDes IP from 1G to 100G data rates offering superior performance and power....
1149
0.0
112Gbps XSR SerDes IP on TSMC 12nm
Credo is a world leading SerDes Technology Company offers silicon proven SerDes IP from 1G to 112G data rates and the first in the industry to demo...
1150
0.0
112Gbps XSR SerDes IP on TSMC 5/4nm
Credo is a world leading SerDes Technology Company offers silicon proven SerDes IP from “1G to 112G” data rates and the first in the industry to demon...
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