Design & Reuse
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arrow Multi-Protocol PHY (31)
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arrow Serdes (92)
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arrow Other (27)
1899 IP
1151
0.0
112Gbps XSR SerDes IP on TSMC 7/6nm
Credo is a world leading SerDes Technology Company offers silicon proven SerDes IP from “1G to 112G” data rates and the first in the industry to de...
1152
0.0
32-bit, 33 MHz Multifunction Target Interface
The PCI-T32MF implements a target-only PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up t...
1153
0.0
32-bit, 33 MHz PCI Target Interface Core
The main PCI-T32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the u...
1154
0.0
32-bit/33,66Mhz PCI Host Bridge
...
1155
0.0
12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 12SF++
The multi-protocol SerDes PHY includes Peripheral Component Interconnect Express (PCIe) conforming with PCIe 2.0 Base Specification with support for P...
1156
0.0
12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 40LL
The multi-protocol SerDes PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support of P...
1157
0.0
12.5G Multiprotocol Serdes IP, Silicon Proven in TSMC 28HPC+
The multi-protocol SerDes PHY consists of Serial ATA (SATA) conforming with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) c...
1158
0.0
12.5G Multiprotocol Serdes IP, Silicon Proven in UMC 28HPC
The multi-protocol SerDes PHY consists of Serial ATA (SATA) conforming with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) c...
1159
0.0
12.5G Serdes in SMIC 40NLL
Brite Semiconductor‘s Serdes provides 2.5-32Gbps multi-rate SERDES IP which is designed for smooth integration of Multiple SERDES lanes demonstrate go...
1160
0.0
224G Ethernet PHY in Samsung (SF4X)
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
1161
0.0
224G Ethernet PHY IP for TSMC N3P
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
1162
0.0
224G-LR SerDes PHY for TSMC N3E/N3P
224G-LR SerDes PHY enables 1.6T and 800G networks The Cadence 224G SerDes PHY for UALink enables the emerging 1.6T and 800G scale-up networks for hyp...
1163
0.0
224G-LR SerDes PHY for UALink for Intel 18A
224G-LR SerDes PHY enables 1.6T and 800G networks for UALink The Cadence 224G SerDes PHY for UALink enables the emerging 1.6T and 800G scale-up net...
1164
0.0
224G-LR SerDes PHY for UALink for TSMC N3E/N3P
224G-LR SerDes PHY enables 1.6T and 800G networks for UALink The Cadence 224G SerDes PHY for UALink enables the emerging 1.6T and 800G scale-up netwo...
1165
0.0
128 Channel Analog Front-End
PMCC_XCM_64X64_A IP block is a 128 channels analog front-end. The IP block consists of 128 variable gain amplifiers (VGAs), 128 2-bit digitizers, bias...
1166
0.0
I2C Bus Master / Slave Controller Interface with FIFO
The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many device...
1167
0.0
I2C Bus Master Controller Core
The I2C-MS core is a controller for the Inter-Integrated Circuit (I2C) bus. The highly configurable core can implement an I2C bus master, slave, or a ...
1168
0.0
I2C Host / Device Bus Controller
The synchronous I2C interface is a block that interconnects an APB bus. The APB - I2C Bridge interfaces to the APB bus on the system side and the I2C ...
1169
0.0
I2C Master / Slave Controller with FIFO (AXI & AXI-Lite Bus)
The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many device...
1170
0.0
I2C Master Controller w/FIFO (AHB & AHB-Lite Bus)
The Digital Blocks DB-I2C-M-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AP...
1171
0.0
I2C Master Controller w/FIFO (AXI & AXI-Lite Bus)
The Digital Blocks DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AX...
1172
0.0
I2C Master IP
SmartDV’s I2C Master IP is a silicon-proven, feature-rich solution designed to enable robust, reliable serial communication across a wide range of emb...
1173
0.0
I2C Slave Controller - Low Power, Low Noise Config with APB Interface
The Digital Blocks DB-I2C-S-SCL-CLK-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA...
1174
0.0
I2C Slave Controller w/FIFO (AHB Bus)
The Digital Blocks DB-I2C-S-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0/3.0...
1175
0.0
I2C Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I2C-S-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0 APB...
1176
0.0
I2C Slave Controller w/FIFO (AXI Bus)
The Digital Blocks DB-I2C-S-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 4/3 AXI...
1177
0.0
I2C Slave Controller with User Register Array / Memory / FIFO / AMBA Interface
The DB-I2C-S-REG is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs interfacing to user registers while autonomous i...
1178
0.0
I2C Slave IP
SmartDV’s I2C Slave IP is a silicon-proven solution for implementing Inter-Integrated Circuit (I2C) protocol slave functionality in a wide range of em...
1179
0.0
I2C Slave To AHB Bridge IP
SmartDV’s I2C Slave to AHB Bridge IP is a silicon-proven solution designed to seamlessly interface low-speed I2C-based peripherals with high-performan...
1180
0.0
I2C Slave To AXI Bridge IP
SmartDV’s I2C Slave to AXI Bridge IP is a silicon-proven solution that enables seamless communication between low-speed I2C-based peripherals and high...
1181
0.0
I2C/SMBus Master/Slave Controller w/FIFO (AXI/AHB/APB)
The Digital Blocks DB-I2C-SMBus-MS-AMBA Controller IP Core is an I2C/SMBus Master/Slave Controller, interfacing a microprocessor via the AMBA AXI, AHB...
1182
0.0
I2CM - DI2CM - I2C Bus Interface - Master
The I2C is a two-wire, bi-directional serial bus, that provides a simple and efficient method of short distance data transmission between many devices...
1183
0.0
I2CMS - DI2CMS - I2C Bus Interface - Master/Slave
The DI2CMS is a flexible and robust interface solution that bridges microprocessors with an I2C (Inter-Integrated Circuit) bus, offering support for b...
1184
0.0
I2CS - DI2CS - Slave I2C bus controller with FIFO
The DI2CS core provides an interface between a microprocessor / microcontroller and I2C bus. It can work as: - a slave transmitter or - slave rece...
1185
0.0
I2CSB - DI2CSB - I2C Bus Interface Slave -Base version
The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many device...
1186
0.0
32G LR Multi-Protocol SerDes (MPS) PHY
Designed to meet the power efficiency and performance requirements of next-generation, high-speed wireline and wireless 5G infrastructure The 32G MPS...
1187
0.0
12G Multiprotocol Serdes IP, Silicon Proven in SMIC 14SF+
The multi-protocol SerDes PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support of P...
1188
0.0
32G SerDes PHY IP in 28nm
The 32G SerDes IP enables ultra-fast serial communication at up to 32 Gbps per channel, providing a scalable and production-ready solution for high-pe...
1189
0.0
32G UCIe Standard PHY for TSMC N3P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
1190
0.0
I2S to AHB bridge, following AMBA4 specifications
dos_I2S_AHB_bridge is an I2S to AHB bridge, following AMBA4 specifications...
1191
0.0
M31 MIPI M-PHY v5.0 IP in 5nm for mobile/automotive applications
MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pi...
1192
0.0
I3C
INNOSILICON™ I3C IP is fully compatible with the MIPI I3C and JESD403-1B standard and backward compatible to I2C. It enhances the existing I2C IP by n...
1193
0.0
I3C Master / Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improv...
1194
0.0
I3C Master Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improv...
1195
0.0
I3C Prototyping Kit (HDK) Total IP in a Box
The I3C Total IP in a box HDK gives I3C SoC developers all the resources they need to implement MIPI I3C specifications right out of the box. The HDK...
1196
0.0
I3C Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-S-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improve...
1197
0.0
64G Multi-SerDes
INNOSILICON™ 64G Multi-SerDes PHY IP is a highly configurable PHY capable of supporting speeds up to 64 Gbps within a single lane. The PHY is pre-conf...
1198
0.0
16G Multi-Protocol SerDes (MPS) PHY
Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 1...
1199
0.0
16G Multiproocol Serdes IP, Silicon Proven in TSMC 28HPC+
The multi protocol SerDes PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 4.0, 3.0, 2.0 Base Specification with su...
1200
0.0
16G SerDes in 28nm
The Actt's 16G SerDes IP is a high performance Multi-lane SerDes PHY IP designed for chips that perform high bandwidth data communication while operat...