Design & Reuse
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1891 IP
1301
0.0
I3C Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I3C-S-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improve...
1302
0.0
16G Multi-Protocol SerDes (MPS) PHY
Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 1...
1303
0.0
16G Multiproocol Serdes IP, Silicon Proven in TSMC 28HPC+
The multi protocol SerDes PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 4.0, 3.0, 2.0 Base Specification with su...
1304
0.0
16G SerDes in 28nm
The Actt's 16G SerDes IP is a high performance Multi-lane SerDes PHY IP designed for chips that perform high bandwidth data communication while operat...
1305
0.0
16G Serdes in SMIC 28HKCP
Brite Semiconductor‘s Serdes provides 2.5-32Gbps multi-rate SERDES IP which is designed for smooth integration of Multiple SERDES lanes demonstrate go...
1306
0.0
16G Serdes in SMIC 28HKD 0.9/1.8V
Brite Semiconductor‘s Serdes provides 2.5-32Gbps multi-rate SERDES IP which is designed for smooth integration of Multiple SERDES lanes demonstrate go...
1307
0.0
16G Serdes in SMIC 28HKD 0.9/2.5V
Brite Semiconductor‘s Serdes provides 2.5-32Gbps multi-rate SERDES IP which is designed for smooth integration of Multiple SERDES lanes demonstrate go...
1308
0.0
16G UCIe Advanced PHY for TSMC N3P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
1309
0.0
16G UCIe Advanced PHY for TSMC N4P/N5P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
1310
0.0
16G UCIe Standard PHY for Samsung SF5A
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
1311
0.0
16G UCIe Standard PHY for TSMC N3A Automotive
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
1312
0.0
16G UCIe Standard PHY for TSMC N4P
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
1313
0.0
16G UCIe Standard PHY for TSMC N5A Automotive
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
1314
0.0
16G UCIe Standard PHY for TSMC N7
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance The Cadence® ...
1315
0.0
56G-LR Pam4 SerDes for TSMC N6/N7
56G LR SerDes PHY provides exceptional performance w/ best-in-class power & area, making it ideal for machine learning and 5G The Cadence 56Gbps Long...
1316
0.0
28G Ethernet PHY IP for TSMC N7
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high-end networking and ...
1317
0.0
28G LR Multi-Protocol SerDes (MPS) PHY
Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 2...
1318
0.0
RapidIO EndPoint Controller IP
RapidIO EP interface provides full support for the RapidIO EP synchronous serial interface, compatible with RapidIO Interconnect 2.2 specification. Th...
1319
0.0
SAS Initiator IP
The SAS Initiator IP core is fully compliant with Serial ATA SCSI 5.0 Specification. Through its compatibility, it provides a simple interface to a wi...
1320
0.0
Fast Ethernet 10/100 802.3 MAC with IEEE 1588 PTP Support
The Arasan 10/100 Ethernet Media Access Controller with IEEE 1588 support IP core is compliant to the Ethernet/IEEE 802.3-2008 standard. It also inclu...
1321
0.0
Fast Ethernet 802.3 Media Access Controller (MAC)
The Arasan 10/100 Ethernet Media Access Controller with AHB Interface IP core is compliant to the Ethernet/IEEE 802.3-2008 standard. The 10/100 Ethern...
1322
0.0
SATA 3.0 Host Controller
The Chevin Technology SATA-HC IP block simplifies the integration of high capacity SSDs utilizing SATA I/II/III at 1.5/3/6Gbit/s data rates using Xili...
1323
0.0
SATA Host Controller IP
SATA HOST CONTROLLER core is compliant with SATA version 3.5 specification. Through its compatibility, it provides a simple interface to a wide range...
1324
0.0
SATA Port Multiplier with Sandbox
The IntelliProp IPP-SA128A-PM (SATA Port Multiplier with Sandbox) device is an IP core that provides SATA Port Multiplier functionality with support f...
1325
0.0
Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers
The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Mem...
1326
0.0
PCI Express (PCIe) 6.0 Controller
Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 6.0 provides the logic required to integrate a roo...
1327
0.0
PCI Express (PCIe) 7.0 Controller
Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 7.0 provides the logic required to integrate a roo...
1328
0.0
PCI Master/Slave IP
PCI MASTER SLAVE interface provides full support for the PCI MASTER SLAVE synchronous serial interface, compatible with PCI 2.0 specification. Through...
1329
0.0
PCI Master/Target Interface Core
...
1330
0.0
PCI to AMBA AHB Host Bridge
This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices. The bridge enables high...
1331
0.0
PCI-X Arbiter Supporting 66 / 100 / 133MHz
In PCI-X systems, a central controller is used to manage bus ownership. This controller, called arbiter, selects the next master during The PCIXarbit...
1332
0.0
UCIE 1.0
Support for multiple protocol PCIE/CXL/Streaming...
1333
0.0
PCIe 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
Rambus PCIe 1.1 Controller with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 1.1 ...
1334
0.0
UCIe 1.1 PHY 5nm
The UCI Express Specification Revision 1.1 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, and 16GT/s with a 16-lane co...
1335
0.0
UCIe 2.0 PHY 4nm
The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, 24GT/s and 32GT/s wi...
1336
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 14SF+
The PCIe 2.0 transceiver IP supports all PCIe 2.0 Base applications. It complies with the PIPE 3.0 standard. This IP incorporates high-speed mixed sig...
1337
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 28HKMG
A physical layer (PHY) IP solution for consumer electronics, the PCIe Gen 2 PHY IP allows for customization. The PHY IP complies with the PCIe2.0 fund...
1338
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 40LL
PCIe Gen 2 PHY IP is a physical layer (PHY) IP solution for consumer electronics, that allows for a full featured customization and complies with the ...
1339
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 55LL/SP/EF
PCIe Gen 2.0 PHY IP is a physical layer (PHY) IP solution for mobile, consumer and Enterprise applications that enable for a well equipped customizati...
1340
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
A wide variety of PCIe 2.0 Base applications are available with PCIe 2.0 transceiver IP. It adheres to the PIPE 3.0 standard. In order to enable PCIe ...
1341
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
The whole spectrum of PCIe 2.0 Base applications is offered by PCIe 2.0 transceiver IP. It adheres to the PIPE 3.0 standard. The PCIe 2.0 data rate at...
1342
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 22ULP/ULL
The PCIe2.0 PHY IP is an all-in-one physical layer (PHY) IP solution for mobile and consumer applications. The PHY IP includes mixed-signal circuits t...
1343
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
The PCIe2.0 PHY IP is a fully - featured physical layer (PHY) IP solution for mobile and consumer applications. The PHY IP integrates mixed signal cir...
1344
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 40ULP
The full gamut of PCIe 2.0 Base operations is covered by PCIe 2.0 transceiver IP. It conforms to the PIPE 3.0 standard. This IP combines high-speed mi...
1345
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 55ULP/65ULP
The PCIe2.0 PHY IP is a complete physical layer (PHY) IP solution designed for mobile and consumer applications. Compliant with the PCIe2.0 base speci...
1346
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in TSMC 7nm
A comprehensive selection of PCIe 2.0 Base applications is offered by PCIe 2.0 transceiver IP. It complies with the requirements of PIPE 3.0. In order...
1347
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
The PCIe 2.0 PHY IP presents a configurable physical layer (PHY) IP solution tailored for Consumer Electronics. It combines mixed signal circuits to f...
1348
0.0
PCIe 2.0 Serdes PHY IP, Silicon Proven in UMC 40LP
The full gamut of PCIe 2.0 Base operations is covered by PCIe 2.0 transceiver IP. It conforms to the PIPE 3.0 standard. This IP combines high-speed mi...
1349
0.0
PCIe 2.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with Built-in DMA and Configurable AMBA AXI Interconnect
Rambus PCIe 2.1 Controller with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 2.1 ...
1350
0.0
PCIe 2.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
Rambus PCIe 2.1 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 2.1 Controlle...