Design & Reuse
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1899 IP
1301
0.0
PCIe 6.2 Switch IP Controller
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1302
0.0
PCIe 7.0 Controller (can be configured to support EP, RP, DM, or SW applications)
The configurable and scalable Synopsys Controller IP for PCI Express® (PCIe®) 7.0 supports all required features of the PCI Express 7.0 specification,...
1303
0.0
PCIe 7.0 Controller with AXI
The Rambus PCI Express® (PCIe®) 7.0 Controller with AXI is a configurable and scalable design for ASIC implementations. It is backward compatible to P...
1304
0.0
PCIe 7.0 Integrity and Data Encryption (IDE) Security IP Module
PCI Express is a ubiquitous interface for a wide variety of applications, from connecting accelerators and peripheral devices to data center servers t...
1305
0.0
PCIe 7.0 PHY for TSMC N5
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...
1306
0.0
PCIe 7.0 PHY in Samsung (SF4X)
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...
1307
0.0
UCIe Controller for Streaming Protocols
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...
1308
0.0
PCIE Controller IP
PCIE Controller interface provides full support for the PCIE synchronous serial interface, compatible with PCIE 5.0 specification. Through its PCIE co...
1309
0.0
PCIe Controller Testbench
PCIe Testbench from Rambus emulates a Root Complex device enabling simulation of a PCI Express design. This includes the following features: • R...
1310
0.0
PCIE Gen6 digital controller (Dual Mode)
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE sp...
1311
0.0
PCIE Gen6 digital controller (End Point)
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE sp...
1312
0.0
PCIE Gen6 digital controller (Root Complex)
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE sp...
1313
0.0
PCIe GEN6 PHY
Designed for next-generation PCIe systems, the PCIe GEN6 PHY IP supports data rates up to 64GT/s per lane with advanced PAM4 signaling. It ensures eff...
1314
0.0
PCIe Gen6.0 Retimer
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...
1315
0.0
PCIE Gen7 Controller
Gen7 supports 128Gbps and backward compatible with previous versions of PCIE....
1316
0.0
PCIe Multi-Function Option for DMA IP Cores
The PCI Express specification allows endpoints that incorporate several physical PCIe functions that share the same PCIe connection. Such endpoints ar...
1317
0.0
UCIe PHY IP on TSMC N3P
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
1318
0.0
UCIe PHY on Samsung SF5A
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...
1319
0.0
UCIe PHY on TSMC N3E
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...
1320
0.0
PCIe refclk buffer (14nm)
The output buffer to deliver a differential clock signal from inside chip to outside for PCIe interface...
1321
0.0
PCIe refclk buffer (8nm)
The output buffer to deliver a differential clock signal from inside chip to outside for PCIe interface...
1322
0.0
PCIe Switch for USB4 Hubs, Hosts and Devices
Rambus PCIe Multi-port Switch for USB4 is a customizable, embedded Switch for PCI Express (PCIe) designed for implementations in USB4 devices. A fully...
1323
0.0
UCIe-A PHY for Advanced Package (x64) in Samsung (SF2)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
1324
0.0
UCIe-A PHY for Advanced Package (x64) in Samsung (SF4X)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
1325
0.0
UCIe-A PHY for Advanced Package (x64) in TSMC (N5)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
1326
0.0
UCIe-S PHY for Standard Package (x32) in TSMC (N3P)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
1327
0.0
UCIe/BoW BlueLynx™ Dual Mode PHY and subsystem IP for chiplet interconnect
Blue Cheetah is a leader in Die-to-Die (D2D) interconnect solutions for chiplets in very advanced and low-cost packaging applications. BlueLynx™ is a...
1328
0.0
PCIe2.0 PHY & Controller
The Innosilicon SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datasheet,...
1329
0.0
PCIe2.1 PHY
The Innosilicon SERDES PHY is a highly configurable PHY capable of supporting speeds up to 25Gbps within a single lane. For this particular datasheet,...
1330
0.0
PCIE4 PHY in SMIC 28HKCP
Brite Semiconductor's 16Gbps PCIe PHY and controller solution provide high efficient interconnection that is optimized for PPA performance. The System...
1331
0.0
PCIE4 PHY in SMIC 28HKD 0.9/1.8V
Brite Semiconductor's 16Gbps PCIe PHY and controller solution provide high efficient interconnection that is optimized for PPA performance. The System...
1332
0.0
PCIE4 PHY in SMIC 28HKD 0.9/2.5V
Brite Semiconductor's 16Gbps PCIe PHY and controller solution provide high efficient interconnection that is optimized for PPA performance. The System...
1333
0.0
PCIe4/3/2/1 PHY & Controller
The Innosilicon PCIe4.0 PHY is a highly configurable PHY capable of supporting speeds up to 16Gbps within a single lane. For this particular datasheet...
1334
0.0
PCIe5.0/4.0/3.0 PHY & Controller
INNOSILICON™ PCIe 5.0 IP combines a high-performance controller and PHY, which is fully compliant with PCIe 5.0/4.0/3.0, and PIPE specifications. The ...
1335
0.0
SD4.1 UHS- II PHY IP
SD4.1 UHS-II IP utilizes distinctive SerDes technology to attain a speed of 312MB/s for UHS-II while maintaining low power consumption. This PHY IP is...
1336
0.0
VDC-M (VESA Display Compression-M) Decoder
The Rambus VESA VDC-M 1.2 Decoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliv...
1337
0.0
VDC-M (VESA Display Compression-M) Encoder
The Rambus VESA VDC-M 1.2 Encoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 encoder to deliv...
1338
0.0
VDC-M Decoder IP
VDC-M DECODER core is compliant with standard VESA Display Stream Compression version 1.1/1.2. Through its compatibility, it provides a simple interfa...
1339
0.0
VDC-M Encoder IP
VDC-M ENCODER core is compliant with standard VESA Display Stream Compression version 1.1/1.2. Through its compatibility, it provides a simple interfa...
1340
0.0
eDisplay Port v1.4 Rx PHY IP in 40LL, Silicon Proven in SMIC 40LL
The eDisplay Port v1.4 Rx PHY IP Core caters to chips requiring high-bandwidth communication with minimal power consumption. It serves as a multi-giga...
1341
0.0
eDisplay Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 22ULP
eDP/DP Tx PHY is designed for chips that perform eDP/DP data communication while operating at low power consumption. The main link is a multi-gigabit ...
1342
0.0
eDisplayPort v1.4 Receiver Controller IP Core
This eDisplayPort 1.4 Rx Controller IP Core is a versatile and comprehensive solution designed for easy integration into any SoC or FPGA development. ...
1343
0.0
eDisplayPort v1.4 Transmitter Controller IP Core
This eDisplayPort 1.4 Tx Controller IP Core integrates into any SoC or FPGA development, supporting the eDisplayPort 1.4b specification. It can be imp...
1344
0.0
HDMI - Display Port Combo PHY IP, Silicon Proven in TSMC 28HPC+
The DisPlay Port/HDMI/DVI Receiver is a high performance combo PHY with Display Port Receiver and HDMI Receiver. In DisPlay Port mode, the receiver is...
1345
0.0
HDMI 1.3 Rx PHY & Controller IP, Silicon Proven in TSMC 40LP
HDMI receiver PHY (Physical layer) IP is single-port core which is fully compliant with HDMI 1.3a specification. This HDMI Rx PHY supports from 25MHz ...
1346
0.0
HDMI 1.3 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP
HDMI transmitter PHY (Physical layer) IP core which is fully compliant with HDMI 1.3 specification. The HDMI TX PHY supports from 25MHz to 250MHz pixe...
1347
0.0
HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in GF 65/55LPe
The HDMI receiver PHY (Physical layer), a single-port IP core, fully conforms with HDMI 1.4's requirements. This HDMI RX PHY supports TMDS rates betwe...
1348
0.0
HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in SMIC 65/55SP
The single-port IP core, HDMI receiver PHY (Physical layer), completely complies with HDMI 1.4's specifications. This HDMI RX PHY provides a straightf...
1349
0.0
HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in ST 28FDSOI
The HDMI receiver PHY (Physical layer), a single-port IP core, complies with all the specifications of HDMI 1.4. This HDMI RX PHY provides a straightf...
1350
0.0
HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 65/55GP
A single-port IP core called the HDMI receiver PHY (Physical layer) is completely compliant with HDMI 1.4's specifications. This HDMI RX PHY provides ...