Design & Reuse
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1861 IP
1401
0.0
UDP/IP Hardware Protocol Stack - 40G
The Digital Blocks DB-UDP-IP-40GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 50 GbE net...
1402
0.0
UDP/IP Hardware Protocol Stack - 50G
The Digital Blocks DB-UDP-IP-50GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 50 GbE net...
1403
0.0
IEC 7816 Smart Card IP
The IEC7816 Slave Controller IP Core is full-featured, easy-to-use, synthesizable designs that are easily integrated into any SoC or FPGA development....
1404
0.0
Secure AHB Performance Subsystem - ARM M3
The Silvaco Secure AHB Performance Subsystem is a high-performance AHB subsystem that allows for a high level of hardware and software security. It in...
1405
0.0
Register Indirect RAM Access
The Veriest Register Indirect RAM Access Design IP provides a bridge between the embedded AMBA AHB bus and a configurable number of embedded SRAM devi...
1406
0.0
General-Purpose I/O Controller Core
The GPIO core is used to create functions in a system that are not implemented with dedicated controllers, and require simple input and/or output soft...
1407
0.0
SENT/SAE J2716 Controller
The CSENT core implements a controller for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and also the i...
1408
0.0
SerDes PHY IP(12nm, 14nm, 22nm, 28nm)
M31 SerDes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications. The SerDes IP suppo...
1409
0.0
VESA DSC (Display Stream Compression) 1.2b Video Decoder
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1410
0.0
VESA DSC (Display Stream Compression) 1.2b Video Encoder
...
1411
0.0
VESA DSC 1.2b Decoder IP Core for Xilinx FPGAs
...
1412
0.0
VESA DSC 1.2b Encoder for Xilinx FPGAs
...
1413
0.0
VESA DSC Decoder IP
DSC DECODER core is compliant with standard VESA Display Stream Compression version 1.1/1.2/1.2a. Through its compatibility, it provides a simple inte...
1414
0.0
VESA DSC Encoder IP
DSC ENCODER core is compliant with standard VESA Display Stream Compression version 1.1/1.2/1.2a. Through its compatibility, it provides a simple inte...
1415
0.0
VESA DSC V1.2 Decoder
Arasan’s VESA DSC v1.2 decoder IP core compresses high-definition streams in real time at resolutions ranging from 480 to 8K. The core supports 8, 10,...
1416
0.0
VESA DSC V1.2 Encoder
The Arasan’s VESA DSC v1.2 Encoder IP core compresses high-definition streams in real time at resolutions ranging from 480 to 8K. The core supports 8,...
1417
0.0
VESA VDC-M V1.2 Encoder
Embrace the future of digital media with Arasan's VESA VDC-M v1.2 Encoder. Our groundbreaking product revolutionizes video compression technology, off...
1418
0.0
UFS 3.1 Host Controller compatible with M-PHY 4.1 and UniPro 1.8
The Arasan UFS Host -UniPro IP is a simple, high performance, serial interface used primarily in mobile systems between host processing and NVM mass s...
1419
0.0
UFS Device IP
The SmartDV UFS DEVICE IP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The UFS...
1420
0.0
8G Multiprotocol Serdes IP, Silicon Proven in SMIC 14SF+
High performance SERDES IP designed for chips that perform high bandwidth data communication while operating at low power consumption....
1421
0.0
IGASERT08A, Derivative IP of IGPSERT12A Lane-based 1 - 12.5 Gbps Enterprise Multi-Standard SerDes
The GUC's EMS-PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include 1GE, XAUI, RXAUI, XFI, 10GBase-KR...
1422
0.0
RGB to CCIR 601 / 656 Encoder
The Digital Blocks DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller such as D...
1423
0.0
AHB AES with DMA
The Advanced Encryption Standard (AES) IP Core is a complete hardware implementation encryption/decryption algorithm described in the U.S. Government ...
1424
0.0
AHB Arbiter IP
AHB Arbiter IP core is compliant with AMBA AHB Specification. Through its compatibility, it provides a simple interface to a wide range of low-cost de...
1425
0.0
AHB Channel with Decoder and Data Mux
The AHB Channel provides the necessary infrastructure to connect as many as 7 AHB Slaves (numbered 1-7) to an AHB bus Master. The AHB Channel perform...
1426
0.0
AHB Decoder IP
AHB Decoder IP core is compliant with AMBA AHB Specification. Through its compatibility, it provides a simple interface to a wide range of low-cost de...
1427
0.0
AHB External Bus Interface
The AHB External Bus Interface (EBI) allows a CPU or AHB Master (such as a DMA core) to transmit and receive data to an external device such as an ext...
1428
0.0
AHB Lite to SPI Bridge
The AHB-Lite to SPI Bridge is used to translate 32-bit AHB-Lite Writes and Reads to Writes and Reads over a SPI interface. A custom 32-bit protocol i...
1429
0.0
AHB Low Power Subsystem - ARM M0
The AHB Low Power Subsystem is an AMBA® based system that is useful as the basic digital infrastructure for building low power SOCs. The subsystem co...
1430
0.0
AHB Multilayer Interconnect
The AHB-MLIC is a multi-layer AMBA® AHB bus fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The multilayer fa...
1431
0.0
AHB Multilayer Interconnect IP
AHB AHB Multilayer Interconnect IP core is compliant with AMBA AHB Specification. Through its compatibility, it provides a simple interface to a wide ...
1432
0.0
AHB Performance Subsystem - ARM M0
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional per...
1433
0.0
AHB Performance Subsystem - ARM M3
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional per...
1434
0.0
AHB Single Channel DMA Controller
The DMA is a configurable single channel direct memory access controller. The DMA IP Core is a Verilog HDL design that can be used in ASIC, Structured...
1435
0.0
AHB Subsystem
The AHB-SBS is an integrated, verified, AMBA® 3.0 interconnect and peripherals subsystem ready for embedded applications using processors with AHB bus...
1436
0.0
AHB To APB Bridge IP
AHB2APB Bridge IP core is compliant with AMBA AHB and AMBA APB Specification. Through its compatibility, it provides a simple interface to a wide rang...
1437
0.0
AHB to APB Bus Bridge
The AHB to APB Bridge translates an AHB bus transaction (read or write) to an APB bus transaction. This is accomplished via two small state machines ...
1438
0.0
AHB Triple DES with DMA
The AHB DES/TDES Encryption/Decryption Engine is a configurable core that interfaces to an AHB microprocessor bus. The Controller encrypts or decrypt...
1439
0.0
AHB-Lite to AHB-Lite Asynchronous Bridge
The AHB-Lite to AHB-Lite Asynchronous Bridge translates an AHB-Lite bus transaction (read or write) on one clock domain to an AHB-Lite bus transacti...
1440
0.0
AHB/AXI4-Lite to AXI4-Stream Bridge
The MM2ST IP core bridges the streaming interfaces of a peripheral or accelerator to a memory-mapped AMBA® AHB or AXI4-Lite bus. Designed for ease ...
1441
0.0
AHB2APB Bridge IP
Truechip's AHB2APB Bridge IP provides chip designers and architects, an efficient way to connect Different Bus Protocol based IPs with reduced latency...
1442
0.0
PHY for PCIe 5.0 and CXL for TSMC
Cadence 32G NRZ multi-protocol PHY The Cadence® 32/25Gbps Multi-Link and Multi-Protocol PHY IP for TSMC is a high-performance SerDes operating from 1...
1443
0.0
PHY for PCIe 6.0 and CXL for Samsung
Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®) 6....
1444
0.0
PHY for PCIe 6.0 and CXL for TSMC N4P/N5P
Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®) 6....
1445
0.0
PHY for PCIe 7.0 and CXL for TSMC N3E/N3P
Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®) 7....
1446
0.0
PHY IP for PCIe 6.0 on TSMC N5
The multi-channel Synopsys PHY IP for PCI Express (PCIe) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interface ...
1447
0.0
High Speed Access & Test IP PCIE Version
High speed access for test and in-chip sensor & monitor data throughout the silicon lifecycle. Within the SiliconMAX Platform, High-Speed Access & Tes...
1448
0.0
High Speed Access & Test IP USB Version
High speed access for test and in-chip sensor & monitor data throughout the silicon lifecycle. Within the SiliconMAX Platform, High-Speed Access & Tes...
1449
0.0
Digital FIR filter with APB interface
The eSi-FIR core provides an interface to filter and decimate time interleaved multi-channel data....
1450
0.0
Digital IIR filter with APB interface
A range of 5th to 11th order digital IIR filters for conditioning and optionally decimating data from an external source and to DMA the output into pr...