Design & Reuse
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1899 IP
1451
0.0
MIL STD 1553 Controller IP
SmartDV’s MIL-STD-1553 Controller IP is a silicon-proven solution designed to meet the stringent reliability and interoperability requirements of mili...
1452
0.0
TileLink To AHB Bridge IP
TileLink to AHB Bridge IP core is compliant with SiFive Tilelink and AMBA AHB Specification. Through its compatibility,it provides a simple interface ...
1453
0.0
TileLink To APB Bridge IP
Tilelink2apb Bridge IP core is compliant with SiFive Tilelink and AMBA APB Specification. Through its compatibility, it provides a simple interface to...
1454
0.0
MIPHY Consumer SerDes IP, Silicon Proven in ST 28FDSOI
Consumer Multimedia Applications: Wide support of Consumer PHY standards such as PCIe Gen1/2/3, USB 3.0 Super Speed, JESD204B, SATA Gen 1/2/3 and SGMI...
1455
0.0
MIPI ASPMI Slave IP
SmartDV’s MIPI ASPMI Slave IP is a silicon-proven solution designed to streamline power management communication between system components in mobile a...
1456
0.0
MIPI BIF Master IP
SmartDV’s MIPI BIF (Battery Interface) Master IP is a compact and efficient solution tailored for battery management and communication in mobile and p...
1457
0.0
MIPI BIF Slave IP
SmartDV’s MIPI BIF (Battery Interface) Slave IP is a silicon-proven, compact, and efficient solution designed to enable secure communication between m...
1458
0.0
MIPI C-PHY 2.1 TX/RX, 6nm
InPsytech proudly presents our groundbreaking innovation, the MIPI C-PHY Ver2.1 IP, setting new standards in connectivity solutions. Designed to empow...
1459
0.0
MIPI C-PHY CSI-2 TX+ (Transmitter) IP in TSMC 40ULP
The MXL-CPHY-CSI-2-TX+ is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as a MIPI Master supporting ...
1460
0.0
MIPI C-PHY DSI RX (Transmitter/Host) IP in TSMC 22ULL
The MXL-CPHY-2p5G-DSI-RX-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificati...
1461
0.0
MIPI C-PHY DSI RX IP
Innosilicon MIPI DSI RX IP implements the MIPI C-PHY as well as MIPI DSI protocols. The DSI link protocol specification is a part of group of communic...
1462
0.0
MIPI C-PHY DSI TX IP
Innosilicon MIPI DSI Transmitter implements the DSI protocol as well as MIPI C-PHY protocol. The DSI link protocol specification is a part of group of...
1463
0.0
MIPI C-PHY RX PHY
The Innosilicon MIPI C-PHY provides a C-PHY in a single IP core, which integrates a compatible PHY that supports high speed data receiver, plus a MIPI...
1464
0.0
MIPI C-PHY TX PHY
The Innosilicon MIPI C-PHY provides a C-PHY in a single IP core, which integrates a compatible PHY that supports high speed data receiver, plus a MIPI...
1465
0.0
MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in Samsung (SF2P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1466
0.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes for TSMC 12FFCP
Synopsys’ integrated DesignWare C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and...
1467
0.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in Samsung (SF2P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1468
0.0
MIPI C-PHY v2.0 D-PHY v2.1 RX for TSMC N6
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1469
0.0
MIPI C-PHY v2.0 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (N7, N6)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1470
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) in TSMC 40ULP
The MXL-CDPHY-CSI-2-TX-T-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical layer supporting the MIPI Alliance Specification...
1471
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) IP in TSMC 65LP
The MXL-CPHY-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as a MIPI Master support...
1472
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX 3.5Gsps/trio in TSMC 28nm
The MXL-CDPHY-3p5G-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specifi...
1473
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX 4.5Gsps/trio in TSMC 28nm
The MXL-CDPHY-4p5G-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specifi...
1474
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP 3.5Gsps/2.5Gbps, 2T/2L
The MXL-CDPHY-CSI-2-TX+-40LP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification f...
1475
0.0
MIPI C-PHY/D-PHY Combo CSI-2 TX+ IP in TSMC 40ULP
The MXL-CDPHY-CSI-2-TX+-40ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...
1476
0.0
MIPI C-PHY/D-PHY Combo DSI RX (Receiver) IP in TSMC 28HPC+
The MXL-CPHY-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as MIPI Slave supporting c...
1477
0.0
MIPI C-PHY/D-PHY Combo DSI TX (Transmitter) IP in TSMC 55G
The MXL-CPHY-DPHY-DSI-TX is a high-frequency low-power, high-performance, physical Layer. The PHY is configured as a MIPI Master supporting display in...
1478
0.0
MIPI C-PHY/D-PHY Combo Universal IP in UMC 40LP
The MXL-CPHY-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY can be configured as a MIPI Master or MIPI...
1479
0.0
MIPI C/D COMBO RX HS PHY UMC 28/22nm
Our silicon-proven MIPI C- and D-PHY combo Rx PHY is compliant with Camera Serial Interface (CSI) version 1.2, supporting D-PHY speeds up to 4.5 GHz (...
1480
0.0
MIPI C/D COMBO TX HS PHY UMC 28/22nm
The MIPI C/D combo PHY Tx IP is compliant with the Display Serial Interface (DSI) with D-PHY signaling up to 4.5GHz and C-PHY operating at a symbol ra...
1481
0.0
MIPI C/D COMBO TX PHY, 5nm
The MIPI C/D combo PHY Tx IP is compliant with the Display Serial Interface (DSI) with D-PHY signaling up to 4.5GHz and C-PHY operating at a symbol ra...
1482
0.0
MIPI C/D PHY TX
This MIPI C-PHY & D-PHY combo IP is designed to compliant with the MIPI C-PHY v1.0 & D-PHY v1.2 specifications. It is designed for low power and high-...
1483
0.0
MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 12 FFC
Several production nodes employ C-PHY/D-PHY Combo with the least amount of power and expense. To accommodate a range of applications, users can config...
1484
0.0
MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 16 FFC
In order to use the least amount of power and money, several production nodes use C-PHY/D-PHY Combo. The Combo PHY can be set up by users in either D-...
1485
0.0
MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 22 ULP
In order to use the least amount of power and money, several production nodes use C-PHY/D-PHY Combo. The Combo PHY can be set up by users in either D-...
1486
0.0
MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 28 HPC+
Several production nodes employ C-PHY/D-PHY Combo to consume the least amount of energy and funds. Users can configure the Combo PHY in D-PHY or C-PHY...
1487
0.0
MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 40 LP
Many production nodes use the C-PHY/D-PHY Combo because it uses the fewest resources and energy. Users can configure the Combo PHY in D-PHY or C-PHY m...
1488
0.0
MIPI C/D-PHY Combo Rx IP, Silicon Proven in TSMC 7 FF
Low-power, and low-cost C-PHY/D-PHY Combo in various process nodes. Users are able to configure this Combo PHY into either D-PHY or C-PHY mode to supp...
1489
0.0
MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 12 FFC
C-PHY/D-PHY Combo in various process nodes with low power and cost. To support various applications, users can set up this Combo PHY in either D-PHY o...
1490
0.0
MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 16 FFC
Low power and cost C-PHY/D-PHY Combo in multiple process nodes. Users can configure this Combo PHY in either D-PHY or C-PHY mode to support a variety ...
1491
0.0
MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 22 ULP
C-PHY/D-PHY Combo in numerous process nodes at low cost and power. To accommodate a range of applications, users can set this Combo PHY in either D-PH...
1492
0.0
MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 28 HPC+
C-PHY/D-PHY Combo at low cost and power in several manufacturing nodes. Users have the option of setting this Combo PHY in either D-PHY or C-PHY mode ...
1493
0.0
MIPI C/D-PHY Combo Tx IP, Silicon Proven in TSMC 40 LP
C-PHY/D-PHY Combo in various production nodes at low cost and power. To accommodate a range of applications, users can set this Combo PHY in either D-...
1494
0.0
MIPI C/D-PHY CSI-2 RX IP
Innosilicon CSI-2 Receiver implements MIPI CSI-2 as well as C/D-PHY protocols. The CSI-2 link protocol specification is a part of group of communicati...
1495
0.0
MIPI C/D-PHY RX
The Innosilicon MIPI C/D-PHY RX provides D-PHY and C-PHY in a single IP core. It integrates a compatible PHY that supports high speed data receiver, p...
1496
0.0
MIPI C/D-PHY TX
The Innosilicon MIPI C/D PHY TX integrates a MIPI C-PHY and a MIPI D-PHY in a single IP core, which provides a MIPI high speed data plus low-power low...
1497
0.0
MIPI CSI-2 Receiver
The Arasan CSI-2 Receiver IP Core functions as a MIPI Camera Serial Interface (CSI-2 Combo) Receiver, which interfaces between a peripheral device (Ca...
1498
0.0
MIPI CSI-2 Receiver IP
SmartDV’s MIPI CSI-2 Receiver IP is a silicon-proven solution designed to enable high-speed, low-power camera interfaces across mobile, automotive, Io...
1499
0.0
MIPI CSI-2 Receiver v1.3 Controller IP, Compatible with MIPI C-PHY & D-PHY
The CSI-2 Receiver IP is in charge of handling CSI2 & SMIA protocols, as well as depacking input data to pixels. It also selects the correct destinati...
1500
0.0
MIPI CSI-2 Receiver v2.0 Controller IP, Compatible with MIPI C-PHY & D-PHY
The CSI-2 Receiver IP is in charge of handling CSI2 & SMIA protocols, as well as depacking input data to pixels. It also selects the correct destinati...