Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow AMBA AHB / APB/ AXI (192)
arrow CXL (20)
arrow D2D (1)
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arrow HDMI (88)
arrow I2C (96)
arrow Interlaken (3)
arrow MIL-STD-1553 (3)
arrow MIPI (512)
arrow Multi-Protocol PHY (33)
arrow PCI (240)
arrow RapidIO (6)
arrow SAS (5)
arrow SATA (74)
arrow Serdes (108)
arrow Smart Card (3)
arrow USB (406)
arrow V-by-One (22)
arrow VESA (80)
arrow Other (35)
1933 IP
1701
0.0
DP1.2 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
1702
0.0
DP1.2 Transmitter PHY
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
1703
0.0
DP1.2 Transmitter PHY_40nm
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
1704
0.0
DP1.4 Receiver Controller
This document describes the low power Innosilicon DP 1.4 Receiver controller, which is fully compliant with DP 1.4 specification and eDP 1.4 standard....
1705
0.0
DP1.4 TX PHY
Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...
1706
0.0
Spacewire Codec with AHB host interface
The GRSPW core implements a Spacewire Codec with RMAP support and AMBA host interface. The core implements the Spacewire standard with the protocol id...
1707
0.0
APB Channel with Decoder and Data Mux
The APB Channel provides the necessary infrastructure to connect as many as 16 AHB Slaves (numbered 0-15) to an APB Bus Master. The APB Channel perfo...
1708
0.0
APB I2C master and slave
The eSi-I2C core implements the I2C two-wire protocol. It supports operation as both an I2C master and slave. The I2C is supplied with an AMBA APB sla...
1709
0.0
APB I2C Master/Slave Controller
The I2C Interface provides full support for the two-wire I2C synchronous serial interface, compatible with the ACCESS Bus physical layer, with additio...
1710
0.0
APB Multilayer Interconnect IP
SmartDV’s APB (Advanced Peripheral Bus) Multilayer Interconnect IP enables efficient communication between multiple APB masters and slaves, streamlini...
1711
0.0
APB peripheral implementing the functionality of the ETSI TS 102613 V7.9.0 (2011-03) MAC Layer
The eSi-SWP MAC is an APB peripheral and implements the functionality of the ETSI TS 102 613 V7.9.0 (2011-03) MAC Layer....
1712
0.0
APB SPI (Serial Peripheral Interface) master and slave
The eSi-SPI core is a Serial Peripheral Interface that can be used to implement full-duplex, synchronous, serial communications between ICs. The eSi-S...
1713
0.0
APB Subsystem
The APB-SBS subsystem integrates typical microcontroller peripherals connected on the an AMBA® APB bus with a bridge to AHB or AXI bus. The subsystem ...
1714
0.0
APB to AHB Bridge IP
SmartDV’s APB to AHB Bridge IP enables seamless communication between low-bandwidth peripheral devices on the APB (Advanced Peripheral Bus) and high-p...
1715
0.0
APB to AHB-Lite Asynchronous Bridge
The APB to AHB-Lite Asynchronous Bridge translates an APB bus transaction (read or write) on one clock domain to an AHB-Lite bus transaction on a seco...
1716
0.0
APB to AXI Bridge IP
SmartDV’s APB to AXI Bridge IP enables seamless protocol conversion between the low-bandwidth APB (Advanced Peripheral Bus) and the high-performance A...
1717
0.0
APB UART with optional ISO7816-3
The eSi-UART core can be used to implement asynchronous serial communications. It is ideally suited for implementing RS232 or ISO7816-3 for smartcard ...
1718
0.0
FPGA Proven PCIe GEN6 Controller
PCIe GEN6 Controller IP Delivers data speed up to 64GT/s (Gigatransfers per second) per lane. Multi-channel packet processing and enhanced RAS capabil...
1719
0.0
SPI to AHB - Lite Bridge
The SPI2AHB core implements an SPI slave to AHB-Lite master bridge. It allows an external SPI master to perform read or write access to any memory-map...
1720
0.0
SPI to AHB Lite Bridge
The ISPI Slave to AHB Lite Master is commonly used as a monitor interface to allow external devices to access the internal AHB bus. A SPI Slave to ...
1721
0.0
SPI to AMBA AHB Master Bridge
The Veriest SPI to AMBA AHB Master Bridge Design IP offers a simple solution to provide "backdoor" access from external SPI master devices to the embe...
1722
0.0
SPI to AXI Bridge
The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...
1723
0.0
GPIO General-Purpose I/O Controller Core
The GPIO core is used to create functions in a system that are not implemented with dedicated controllers, and require simple input and/or output soft...
1724
0.0
Hs-Mode I2C Controller - 3.4 Mbps, Master w/FIFO
The Digital Blocks DB-I2C-M-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bus...
1725
0.0
Hs-Mode I2C Controller - 3.4 Mbps, Slave w/FIFO
The Digital Blocks DB-I2C-S-Hs-Mode I2C Slave Controller IP Core interfaces user Registers to an I2C Bus or Memory (SDRAM / SRAM / Flash / FIFO) or an...
1726
0.0
ASA-ML Serdes IP Core in 22nm
The ASA PHY IP Core in 22nm delivers next-generation automotive SerDes connectivity, enabling high-bandwidth, low-latency serial links for advanced au...
1727
0.0
ASA-ML Serdes IP Core in 28nm
The ASA PHY IP Core in 28nm provides scalable and robust SerDes connectivity for advanced automotive SoCs. Supporting the Automotive SerDes Alliance s...
1728
0.0
USB 1.1 Device Controller IP
USB 1.1 Device Controller IP is based on the latest USB 1.1 specification from USB Implementer Forum (USB-IF) and is compatible with the latest xHCI 1...
1729
0.0
USB 1.x Device IP
USB 1.x Device interface provides full support for the USB1.x synchronous serial interface, compatible with USB 1.1 specification. Through its USB1.x ...
1730
0.0
USB 2.0 (LS, FS & HS) On-The-Go IP Core
A 'Dual-Role' USB On-The-Go IP Core that operates as both an USB peripheral or as an USB OTG host in a point-to-point communications with another USB ...
1731
0.0
USB 2.0 Controller
Mature controller solution for OTG and Device applications Certified for compliance with Universal Serial Bus Specification, Revision 2.0, the Cadenc...
1732
0.0
USB 2.0 Device Controller
The Universal Serial Bus Device Controller provides a USB 2.0 function interface accessible from an AMBA-AHB bus interface. The core must be connected...
1733
0.0
USB 2.0 Device Controller IP
We provide highly configurable USB 2.0 device controller IP Cores. Our host, device, and hub offerings are silicon realized and USB-IF certified by ou...
1734
0.0
USB 2.0 Device IP Core
A USB 2.0 Device IP Core that provides high performance small footprint solution for quick and easy implementation of a USB Device interface. The USB...
1735
0.0
USB 2.0 Host (xHCI) Controller IP
We provide highly configurable and scalable USB 2.0 host/ device/dual-mode controller IP Cores for a wide range of applications. The USB 2.0 controlle...
1736
0.0
USB 2.0 Host Controller
The USB 2.0 Host Controller core (GRUSBHC) provides a link between the AMBA on-chip bus and the Universal Serial Bus (USB). The host controller suppor...
1737
0.0
USB 2.0 OTG Dual Role Device
The Arasan USB 2.0 OTG DRD IP Core is compliant with the OTG Supplement Rev. 1.0a. The USB 2.0 OTG DRD core supports the Host Controller, Device Contr...
1738
0.0
USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core
Our company offers a highly configurable and adaptable USB 2.0 OTG controller IP core, suitable for a wide range of applications. This controller adhe...
1739
0.0
USB 2.0 PHY for Samsung
Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power The ubiquity of USB 2.0 in devices makes it nearly mandatory ...
1740
0.0
USB 2.0 PHY for Samsung 7LPP
Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power The ubiquity of USB 2.0 in devices makes it nearly mandatory fo...
1741
0.0
USB 2.0 PHY for TSMC
Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power The ubiquity of USB 2.0 in devices makes it nearly mandatory ...
1742
0.0
USB 2.0 PHY IBM 180
The Arasan USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specification, for use...
1743
0.0
USB 2.0 PHY IP, Silicon Proven in SMIC 12SF++
A full physical layer (PHY) IP solution designed for outstanding performance and minimal power consumption is the USB2.0 PHY IP. The USB2.0 IP impleme...
1744
0.0
USB 2.0 PHY IP, Silicon Proven in SMIC 14SF+
The USB2.0 PHY IP is a comprehensive physical layer (PHY) IP solution created for exceptional performance and low power consumption. The High-Speed US...
1745
0.0
USB 2.0 PHY IP, Silicon Proven in SMIC 40LL
The USB 2.0 PHY IP Core is a complete solution for the physical layer (PHY) that prioritizes both high performance and low power consumption. This ver...
1746
0.0
USB 2.0 PHY IP, Silicon Proven in SMIC 55LL
The USB2.0 PHY IP is a comprehensive physical layer (PHY) IP solution created for exceptional performance and low power consumption. The High-Speed US...
1747
0.0
USB 2.0 PHY IP, Silicon Proven in TSMC 12FFC
The whole physical layer (PHY) IP solution for USB 2.0 was designed for outstanding performance and low power consumption. The High-Speed USB 2.0 Tran...
1748
0.0
USB 2.0 PHY IP, Silicon Proven in TSMC 16FFC
The entire physical layer (PHY) IP solution for USB 2.0 was created to provide exceptional performance and consume little power. The USB2.0 IP impleme...
1749
0.0
USB 2.0 PHY IP, Silicon Proven in TSMC 22ULP
The USB 2.0 PHY IP Core is a full physical layer (PHY) IP solution created for excellent performance and low power consumption. The High-Speed USB 2.0...
1750
0.0
USB 2.0 PHY IP, Silicon Proven in TSMC 28HPC+
The USB2.0 PHY IP is an entire physical layer (PHY) IP solution built for high performance and low power consumption. For usage with either hosts, dev...