Design & Reuse
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1926 IP
1701
0.0
Globalfoundries 22nm MIPI D-PHY Rx only V1.1@1.5GHz
Arasan 2nd Generation MIPI D-PHY v1.1 Rx IP supporting speeds of up to 1.5 Gbps on GF 22nm process technology for SoC designs. Arasan’s D-PHY IP is av...
1702
0.0
Globalfoundries 22nm MIPI D-PHY Tx only V1.2@2.5GHz
Arasan Chip Systems standalone MIPI D-PHY(SM) Transmit only for Globalfoundries 22nm FinFET process nodes. Arasan's standalone D-PHY Tx only for Glo...
1703
0.0
Globalfoundries 22nm MIPI D-PHY Tx only V1.1@1.5GHz
Arasan 2nd Generation MIPI D-PHY v1.1 Tx IP supporting speeds of up to 1.5 Gbps on GF 22nm process technology for SoC designs. Arasan’s D-PHY IP is av...
1704
0.0
Globalfoundries 22nm MIPI D-PHY Universal Tx-Rx V1.1@1.5GHz
Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on GF 22nm process technology for SoC designs. Arasan’s D-PHY IP is avail...
1705
0.0
Globalfoundries 22nm MIPI D-PHY Universal Tx-Rx V1.2 @ 2.5GHz
Arasan Chip Systems announces the immediate availability of its MIPI D-PHY(SM) Globalfoundries 22nm FinFET process nodes. Arasan's D-PHY Global Foun...
1706
0.0
DMA AXI4-Stream Interface to AXI Memory Map Address Space
Digital Blocks DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE Verilog RTL IP Core accepts AXI4-Stream data and control input, converts the control TID to a AXI4 Mem...
1707
0.0
Smart Network-on-Chip (NoC) IP
AI-Enhanced Automation for Smarter SoC Design FlexGen™ by Arteris redefines how SoC designers create Network-on-Chip IP by introducing cutting-edge...
1708
0.0
AMBA AHB Address Trapper
The Veriest AMBA AHB Address Trapper Design IP provides a mechanism for debug of an AMBA AHB bus. This gives added visibility to the software in order...
1709
0.0
AMBA AHB Device/Host Bridge
This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices. The bridge supports Hos...
1710
0.0
AMBA AHB Simple Master Bridge
The Veriest AMBA AHB Simple Master Bridge Design IP provides a bridge between the embedded AMBA AHB bus master and a simplified generic local bus. The...
1711
0.0
AMBA AHB Slave to Local Interface Bridge
The Veriest AMBA AHB Slave Bridge Design IP offers a simple solution to provide a bridge between the embedded AMBA AHB bus and a simplified generic lo...
1712
0.0
AMBA AHB to APB Bus Bridge Core
The AHB2APB implements an AHB to APB bus bridge, allowing the connection of peripherals with an APB interface to an AHB bus. The highly-configurable...
1713
0.0
AMBA AXI Data Prefetch Buffer
The Veriest AMBA AXI Data Prefetch Buffer Design IP provides a mechanism read / prefetch contiguous data over the AXI from a memory such as DDR SDRAM...
1714
0.0
AMBA AXI Data Writer Spreader
The Veriest AMBA AXI Data Writer Speader Design IP provides a mechanism to write data over the AXI to a memory such as DDR SDRAM in which the data ma...
1715
0.0
AMBA AXI Performance Monitor
The Veriest AMBA AXI Performance Monitor Design IP provides a mechanism for analysis of embedded AMBA AXI fabric latency. This gives added visibility ...
1716
0.0
UMC MIPI D-PHY Tx 2.5G and MIPI D-PHY Rx 2.5G (Automotive Interface IP)
Egis Technology Inc., an Automotive interface IP solution provider, introduces its latest Automotive High-Speed Interface IP Series, designed to meet ...
1717
0.0
ONFI 2.3 NAND Flash Controller
The Arasan ONFI 2.3 NAND Flash Controller IP Core is a full featured, easy to use, synthesizable core, easily integrated into any SoC or FPGA developm...
1718
0.0
INTC IP
Interrupt Controller interface provides full support for programmable edge triggered (rising, falling) or sensitive, compatible with Interrupt Control...
1719
0.0
Interface Controller - PHY IP
The UCIE PHY IP is a market leading, extremely low-power, low-latency interface IP for very high bandwidth connections between two dies that are on th...
1720
0.0
Interlaken IP
Interlaken interface provides full support for the Interlaken synchronous serial interface, compatible with Interlaken version 1.2 specification. Thro...
1721
0.0
Internal Synchronous SRAM Controller Core
The SRAM-CTRL implements a SRAM Controller providing a standard AHB/APB interface to translate AHB/APB bus reads and writes into reads and writes with...
1722
0.0
Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
Rambus CXL 2.0 Controller with AXI is a parameterizable Compute Express Link (CXL) controller Soft IP designed for ASIC and FPGA implementation. Rambu...
1723
0.0
Low Power Dual PHY for UCIe low cost robust Chiplets
YorChip UniPHY™ Dual PHY is a flexible version of YorChip’s multi-protocol PHY which supports UCIe and BOW standards. The Dual PHY’s unique feature ...
1724
0.0
DP/eDP PHY + Controller
INNOSILICON™ DP/eDP IP is designed for transmitting or receiving video and audio signals between the video source devices and display devices. It is f...
1725
0.0
DP1.1 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
1726
0.0
DP1.2 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
1727
0.0
DP1.2 Transmitter PHY
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
1728
0.0
DP1.2 Transmitter PHY_40nm
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
1729
0.0
DP1.4 Receiver Controller
This document describes the low power Innosilicon DP 1.4 Receiver controller, which is fully compliant with DP 1.4 specification and eDP 1.4 standard....
1730
0.0
DP1.4 TX PHY
Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...
1731
0.0
APB Channel with Decoder and Data Mux
The APB Channel provides the necessary infrastructure to connect as many as 16 AHB Slaves (numbered 0-15) to an APB Bus Master. The APB Channel perfo...
1732
0.0
APB I2C master and slave
The eSi-I2C core implements the I2C two-wire protocol. It supports operation as both an I2C master and slave. The I2C is supplied with an AMBA APB sla...
1733
0.0
APB I2C Master/Slave Controller
The I2C Interface provides full support for the two-wire I2C synchronous serial interface, compatible with the ACCESS Bus physical layer, with additio...
1734
0.0
APB Multilayer Interconnect IP
SmartDV’s APB (Advanced Peripheral Bus) Multilayer Interconnect IP enables efficient communication between multiple APB masters and slaves, streamlini...
1735
0.0
APB peripheral implementing the functionality of the ETSI TS 102613 V7.9.0 (2011-03) MAC Layer
The eSi-SWP MAC is an APB peripheral and implements the functionality of the ETSI TS 102 613 V7.9.0 (2011-03) MAC Layer....
1736
0.0
APB SPI (Serial Peripheral Interface) master and slave
The eSi-SPI core is a Serial Peripheral Interface that can be used to implement full-duplex, synchronous, serial communications between ICs. The eSi-S...
1737
0.0
APB Subsystem
The APB-SBS subsystem integrates typical microcontroller peripherals connected on the an AMBA® APB bus with a bridge to AHB or AXI bus. The subsystem ...
1738
0.0
APB to AHB Bridge IP
SmartDV’s APB to AHB Bridge IP enables seamless communication between low-bandwidth peripheral devices on the APB (Advanced Peripheral Bus) and high-p...
1739
0.0
APB to AHB-Lite Asynchronous Bridge
The APB to AHB-Lite Asynchronous Bridge translates an APB bus transaction (read or write) on one clock domain to an AHB-Lite bus transaction on a seco...
1740
0.0
APB to AXI Bridge IP
SmartDV’s APB to AXI Bridge IP enables seamless protocol conversion between the low-bandwidth APB (Advanced Peripheral Bus) and the high-performance A...
1741
0.0
APB UART with optional ISO7816-3
The eSi-UART core can be used to implement asynchronous serial communications. It is ideally suited for implementing RS232 or ISO7816-3 for smartcard ...
1742
0.0
FPGA Proven PCIe GEN6 Controller
PCIe GEN6 Controller IP Delivers data speed up to 64GT/s (Gigatransfers per second) per lane. Multi-channel packet processing and enhanced RAS capabil...
1743
0.0
SPI Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...
1744
0.0
SPI Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...
1745
0.0
SPI Master Controller w/FIFO (AHB & AHB-Lite Bus)
The Digital Blocks DB-SPI-M is a Serial Port Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and...
1746
0.0
SPI Master Controller w/FIFO (APB Bus)
The Digital Blocks DB-SPI-M is a Serial Port Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and...
1747
0.0
SPI to AHB Lite Bridge
The ISPI Slave to AHB Lite Master is commonly used as a monitor interface to allow external devices to access the internal AHB bus. A SPI Slave to ...
1748
0.0
SPI to AHB-Lite Bridge
The SPI2AHB core implements an SPI slave to AHB-Lite master bridge. It allows an external SPI master to perform read or write access to any memory-map...
1749
0.0
SPI to AMBA AHB Master Bridge
The Veriest SPI to AMBA AHB Master Bridge Design IP offers a simple solution to provide "backdoor" access from external SPI master devices to the embe...
1750
0.0
SPI to AXI Bridge
The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...