Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow AMBA AHB / APB/ AXI (186)
arrow CXL (20)
arrow D2D (8)
arrow Gen-Z (6)
arrow HDMI (96)
arrow I2C (97)
arrow Interlaken (2)
arrow MIL-STD-1553 (3)
arrow MIPI (531)
arrow Multi-Protocol PHY (34)
arrow PCI (247)
arrow RapidIO (7)
arrow SAS (6)
arrow SATA (75)
arrow Serdes (108)
arrow Smart Card (7)
arrow UFS (8)
arrow USB (412)
arrow V-by-One (22)
arrow VESA (79)
arrow Other (71)
2025 IP
1751
0.0
UMC MIPI D-PHY Tx 2.5G and MIPI D-PHY Rx 2.5G (Automotive Interface IP)
Egis Technology Inc., an Automotive interface IP solution provider, introduces its latest Automotive High-Speed Interface IP Series, designed to meet ...
1752
0.0
One-Wire Interface Controller IP
SmartDV's One-Wire Interface Controller IP is a silicon-proven, fully featured single-wire serial communication solution purpose-built for SoC designs...
1753
0.0
ONFI 2.3 NAND Flash Controller
The Arasan ONFI 2.3 NAND Flash Controller IP Core is a full featured, easy to use, synthesizable core, easily integrated into any SoC or FPGA developm...
1754
0.0
Uni-directional AMBA AHB to AHB bridge
The Uni-directional AHB to AHB bridge is used to connect two AHB buses clocked by synchronous clocks with any frequency ratio. The bridge is connected...
1755
0.0
Internal Synchronous SRAM Controller Core
The SRAM-CTRL implements a SRAM Controller providing a standard AHB/APB interface to translate AHB/APB bus reads and writes into reads and writes with...
1756
0.0
Interrupt Controller IP
SmartDV's Interrupt Controller IP is a silicon-proven, fully featured interrupt management solution purpose-built for SoC designs requiring flexible, ...
1757
0.0
Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
Rambus CXL 2.0 Controller with AXI is a parameterizable Compute Express Link (CXL) controller Soft IP designed for ASIC and FPGA implementation. Rambu...
1758
0.0
Configurable MIPI CSI-2 v1.1 Receiver Controller Whitebox IP
This MIPI CSI-2 v1.1 Rx Controller IP implements the digital protocol-receive functions required between a MIPI D-PHY v1.1 interface and an SoC image-...
1759
0.0
Controller for MIPI Soundwire
Audio data transport The Cadence® IP Family for MIPI® Protocols delivers area-optimized interface IP with the low power and high performance requir...
1760
0.0
DP 1.4 / eDP v1.4b TXPHY (14nm) 14LPU
The eDP v1.4b TX PHY IP consists of a hard macro architecture supporting embedded DisplayPort v1.4 specification with data rates up to 8.1 Gbps per la...
1761
0.0
DP 1.4 / eDP v1.4b TXPHY (8nm) 8LPU
The eDP v1.4b TX PHY IP consists of a hard macro architecture supporting embedded DisplayPort v1.4 specification with data rates up to 8.1 Gbps per la...
1762
0.0
DP 2.1a / eDP v2.0 RXPHY (4nm) SF4X
The DP/eDP RX PHY consists of hardmacro PHY compliant to DP v2.1a and eDP v2.0 specification, supporting maximum data rate of up to UHBR(20Gbps) opera...
1763
0.0
DP 2.1a / eDP v2.0 TXPHY (4nm) SF4X
The DP/eDP TX PHY consists of hardmacro PHY compliant to DP v2.1a and eDP v2.0 specification, supporting maximum data rate of up to UHBR(20Gbps) opera...
1764
0.0
DP/eDP PHY + Controller
INNOSILICON™ DP/eDP IP is designed for transmitting or receiving video and audio signals between the video source devices and display devices. It is f...
1765
0.0
DP1.1 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
1766
0.0
DP1.2 RX PHY
Innosilicon DP RX PHY is designed to receive and recover the video, audio and auxiliary data from a DP or eDP source device for display applications. ...
1767
0.0
DP1.2 Transmitter PHY
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
1768
0.0
DP1.2 Transmitter PHY_40nm
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
1769
0.0
DP1.4 Receiver Controller
This document describes the low power Innosilicon DP 1.4 Receiver controller, which is fully compliant with DP 1.4 specification and eDP 1.4 standard....
1770
0.0
DP1.4 TX PHY
Innosilicon eDP TX PHY is designed to transmit video, audio, and auxiliary data from a system host device to a display device for display applications...
1771
0.0
Spacewire Codec with AHB host interface
The GRSPW core implements a Spacewire Codec with RMAP support and AMBA host interface. The core implements the Spacewire standard with the protocol id...
1772
0.0
APB Channel with Decoder and Data Mux
The APB Channel provides the necessary infrastructure to connect as many as 16 AHB Slaves (numbered 0-15) to an APB Bus Master. The APB Channel perfo...
1773
0.0
APB I2C master and slave
The eSi-I2C core implements the I2C two-wire protocol. It supports operation as both an I2C master and slave. The I2C is supplied with an AMBA APB sla...
1774
0.0
APB I2C Master/Slave Controller
The I2C Interface provides full support for the two-wire I2C synchronous serial interface, compatible with the ACCESS Bus physical layer, with additio...
1775
0.0
APB Multilayer Interconnect IP
SmartDV's APB Multilayer Interconnect IP is a silicon-proven, high-performance AMBA APB bus fabric solution purpose-built for SoC designs requiring fl...
1776
0.0
APB peripheral implementing the functionality of the ETSI TS 102613 V7.9.0 (2011-03) MAC Layer
The eSi-SWP MAC is an APB peripheral and implements the functionality of the ETSI TS 102 613 V7.9.0 (2011-03) MAC Layer....
1777
0.0
APB SPI (Serial Peripheral Interface) master and slave
The eSi-SPI core is a Serial Peripheral Interface that can be used to implement full-duplex, synchronous, serial communications between ICs. The eSi-S...
1778
0.0
APB Subsystem
The APB-SBS subsystem integrates typical microcontroller peripherals connected on the an AMBA® APB bus with a bridge to AHB or AXI bus. The subsystem ...
1779
0.0
APB to AHB Bridge IP
SmartDV's APB to AHB Bridge IP is a silicon-proven, fully featured protocol bridge solution purpose-built for SoC designs requiring seamless APB-to-AH...
1780
0.0
APB to AHB-Lite Asynchronous Bridge
The APB to AHB-Lite Asynchronous Bridge translates an APB bus transaction (read or write) on one clock domain to an AHB-Lite bus transaction on a seco...
1781
0.0
APB to AXI Bridge IP
SmartDV's APB to AXI Bridge IP is a silicon-proven, fully featured protocol bridge solution purpose-built for SoC designs requiring seamless APB-to-AX...
1782
0.0
APB UART with optional ISO7816-3
The eSi-UART core can be used to implement asynchronous serial communications. It is ideally suited for implementing RS232 or ISO7816-3 for smartcard ...
1783
0.0
LPC Device IP
SmartDV's LPC (Low Pin Count) Device IP is a silicon-proven solution designed to enable reliable, low-bandwidth communication between embedded control...
1784
0.0
LPC Host IP
SmartDV's LPC (Low Pin Count) Host IP is a silicon-proven solution that enables efficient communication with LPC-compliant peripheral devices. Designe...
1785
0.0
SPDIF Receiver IP
SmartDV's SPDIF Receiver IP is a silicon-proven, fully featured Sony/Philips Digital Interface receiver solution purpose-built for SoC designs requiri...
1786
0.0
SPDIF Transmitter IP
SmartDV's SPDIF Transmitter IP is a silicon-proven, fully featured Sony/Philips Digital Interface transmitter solution purpose-built for SoC designs r...
1787
0.0
FPGA Proven PCIe GEN6 Controller
PCIe GEN6 Controller IP Delivers data speed up to 64GT/s (Gigatransfers per second) per lane. Multi-channel packet processing and enhanced RAS capabil...
1788
0.0
SPI Master IP
SmartDV's SPI Master IP is a silicon-proven, fully featured Serial Peripheral Interface master solution purpose-built for SoC designs requiring flexib...
1789
0.0
SPI Slave IP
SmartDV's SPI Slave IP is a silicon-proven, fully featured Serial Peripheral Interface slave solution purpose-built for SoC designs requiring reliable...
1790
0.0
SPI Slave to AHB Bridge IP
SmartDV's SPI Slave to AHB Bridge IP is a silicon-proven, fully featured serial peripheral interface bridge solution purpose-built for SoC designs req...
1791
0.0
SPI Slave to AXI Bridge IP
SmartDV's SPI Slave to AXI Bridge IP is a silicon-proven, fully featured serial peripheral interface bridge solution purpose-built for SoC designs req...
1792
0.0
SPI to AHB - Lite Bridge
The SPI2AHB core implements an SPI slave to AHB-Lite master bridge. It allows an external SPI master to perform read or write access to any memory-map...
1793
0.0
SPI to AHB Lite Bridge
The ISPI Slave to AHB Lite Master is commonly used as a monitor interface to allow external devices to access the internal AHB bus. A SPI Slave to ...
1794
0.0
SPI to AMBA AHB Master Bridge
The Veriest SPI to AMBA AHB Master Bridge Design IP offers a simple solution to provide "backdoor" access from external SPI master devices to the embe...
1795
0.0
SPI to AXI Bridge
The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...
1796
0.0
GPIO General-Purpose I/O Controller Core
The GPIO core is used to create functions in a system that are not implemented with dedicated controllers, and require simple input and/or output soft...
1797
0.0
SPMI Whitebox Controller IP
This MIPI SPMI 2.0 Peripheral Controller IP implements the device-side functions of the SPMI power-management bus. It supports the two-wire SCLK/SDATA...
1798
0.0
Hs-Mode I2C Controller - 3.4 Mbps, Master w/FIFO
The Digital Blocks DB-I2C-M-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bus...
1799
0.0
Hs-Mode I2C Controller - 3.4 Mbps, Slave w/FIFO
The Digital Blocks DB-I2C-S-Hs-Mode I2C Slave Controller IP Core interfaces user Registers to an I2C Bus or Memory (SDRAM / SRAM / Flash / FIFO) or an...
1800
0.0
ASA-ML Serdes IP Core in 22nm
The ASA PHY IP Core in 22nm delivers next-generation automotive SerDes connectivity, enabling high-bandwidth, low-latency serial links for advanced au...