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1877 IP
1801
0.0
USB4 PHY IP for TSMC N3E
The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router,...
1802
0.0
MSC Microsecond Channel (Plus) high-speed controller
The MSC-CTRL IP core implements a high-speed serial interface controller designed to connect a microcontroller or SoC to external power devices or sen...
1803
0.0
CSI2 RX; Camera Serial Interface, MIPI Compliant
The CSI2 Receiver IP Interfaces between Camera module which has the transmitter and the application processor. The CSI2 Receiver IP is fully compliant...
1804
0.0
CSI2 TX; Camera Serial Interface, MIPI Compliant
CSI2 – TX is part of HCL’s MIPI® compliant offerings. The CSI2 Transmitter IP supports Pixel Interface on the camera sensor side and the DPHY is suppo...
1805
0.0
HSIC PHY
The Innosilicon HSIC PHY is fully compliant with the High-Speed Inter-Chip Supplement to the USB 2.0 Specification. By stripping off all the legacy US...
1806
0.0
ASIL-B Ready ISO 26262 Certified VESA DSC (Display Stream Compression) 1.1 Encoder
The VESA DSC 1.1 Encoder IP Core for automotive displays implements a fully compliant VESA DSC 1.1 encoder. It contains additional safety features to ...
1807
0.0
TSMC 12FFC Lane-based 1.25 - 22.5 Gbps Enterprise Multi-Standard SerDes
The GUC's EMS-PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include PCIe Gen1-Gen4, SAS-4 G1-G5 and a...
1808
0.0
TSMC CLN12FFC Lane-based 1.5 - 16 Gbps Enterprise Multi-Standard SerDes
The GUC's EMS-PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include PCIe Gen1-Gen4,SAS-3 G1-G4, SATA-...
1809
0.0
TSMC CLN28HPC+ Derivative IP of IGASERT06A Enterprise Multi-Standard SerDes
The GUC's Quad-Lane EMS-XT PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include CEI-28G-VSR, CEI-25G...
1810
0.0
TSMC CLN7FF Lane-based 1.5 – 22.5 Gbps Enterprise Multi-Standard SerDes
The GUC's EMS-PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include PCIe Gen1-Gen4, SAS-4 G1-G5 and a...
1811
0.0
TSMC N7FF 25.78125Gbps Enterprise SerDes
The receiver equalizes and recovers incoming serial data and de-serializes the data stream into selectable 32/40/64 bit-wide data bus. The transmitter...
1812
0.0
ISO 7816 based digital controller for integrated circuit card compliant with ETSI TS 102 221 and EMV 2000 standards
Smart card controller core is compliant to ISO 7816 3 specification. The core is a technology independent, fully synchronous design. The controller fu...
1813
0.0
ISO 7816 based Smart Card Reader IP
The DSMART is a fast, versatile and cost-competitive core intended for smart card reader applications. It provides a communication interface with a sm...
1814
0.0
eSPI & SPI Master Controller w/FIFO
The Digital Blocks DB-eSPI-SPI-M-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI)...
1815
0.0
eSPI & SPI Slave Controller w/FIFO
The Digital Blocks DB-eSPI-SPI-S-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI)...
1816
0.0
MST Topology Management Stack
The Trilinear Technologies DisplayPort Multi-stream Transport (MST) Topology Management Software enables developers to accelerate software development...
1817
0.0
Multi-Function PCI Master/Target Interface Core
The PCI-M32MF implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up...
1818
0.0
Multi-Video-Source Multiplexing Serial Video Transmitter for MIPI CSI2
The SVT-CS4AP2 supports MIPI CSI2 over MIPI D-PHY. It allows mutilplexing of up to 10 video sources into a CSI2 output stream...
1819
0.0
Multiplexing transceiver with 4 CSI2 inputs and a single CSI2 output
This IP multiplexes inputs from up to 4 CSI2 cameras, each with up to 4 data lanes, to a single CSI2 output stream, with up to 4 lanes. It comprises o...
1820
0.0
Multiprotocol 10G PHY in TSMC (16nm, N7)
The multi-lane Synopsys IP Multi-Protocol 10G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio, meeting the growing need...
1821
0.0
eUSB 2.0 PHY in TSMC (N5, N4P, N4C, N3E, N3P, N2P)
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
1822
0.0
eUSB 2.0 PHY in TSMC (N5A, N3A) for Automotive
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
1823
0.0
eUSB2 PHY
The industry’s most advanced process nodes do not support 3.3V signaling and 5V tolerance as required by the USB 2.0 specification. 3.3V signaling was...
1824
0.0
eUSB2 PHY on Samsung SF4X
The Embedded USB 2.0 PHY is a High speed System-on-Chip (SoC) integrated transceiver IP in advanced process that implements the Intel® UTMI standard. ...
1825
0.0
eUSB2V2 PHY
Low voltage USB 2.0 supporting 4.8Gbps eUSB2V2 is primarily a performance enhancement to eUSB2 native mode to provide more bandwidth for peripherals,...
1826
0.0
eUSB2V2 PHY in TSMC (22nm)
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0...
1827
0.0
LVDS Tx IP, Silicon Proven SMIC 14SF+
The Low-Voltage Differential Signaling Transmitter IP Core provides a very High speed and Low power differential data transfer for Video interface and...
1828
0.0
SWI3S Manager core IP
Arasan’s SWI3S (SoundWire I3S Interface) Manager Controller Core IP implements the link protocol to communicate in half-duplex fashion to transfer the...
1829
0.0
SWI3S Peripheral core IP
Arasan’s SWI3S (SoundWire I3S Interface) Peripheral Controller Core IP implements the link protocol to communicate in half-duplex fashion to transfer ...
1830
0.0
AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA
The Digital Blocks DB-SPI-FLASH-CTRL is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting access to Single/Dual/Quad SPI Flash...
1831
0.0
AXI Bridge for PCIe IP Core
The AXI Bridge for PCIe IP core is the IP solution with a powerful mix of multiple industry standard memory mapped AXI Interfaces.The AXI Bridge IP c...
1832
0.0
AXI Interconnect Fabric
The AXI Interconnect provides the necessary infrastructure to connect as many as 8 shared AXI Slaves to as many as 4 AXI Bus Masters. AXI defines 5...
1833
0.0
AXI Interface Core
Rambus’s AXI Interface Core is designed for use in applications requiring ARM’s Advanced eXtensible Interface (AXI). The core accepts write and rea...
1834
0.0
AXI Multilayer Interconnect
The AXI-MLIC is an AMBA® AXI bus interconnect fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The AXI fabric ...
1835
0.0
AXI Multilayer Interconnect IP
SmartDV’s AXI Multilayer Interconnect IP is a high-throughput, silicon-proven solution designed to manage complex on-chip communication between multip...
1836
0.0
AXI Subsystem
The AXI-SBS is an integrated, verified, AMBA® compliant hardware/software system ready for embedded applications using processors with AXI4 interfaces...
1837
0.0
AXI to AHB Bridge IP
SmartDV’s AXI to AHB Bridge IP enables seamless interoperability between AMBA AXI and AMBA AHB protocols, allowing efficient data transfer across syst...
1838
0.0
AXI to AHB Lite Bus Bridge
The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...
1839
0.0
AXI to APB Bridge
The AXI2APB implements a bridge between AXI and APB buses, allowing the connection of peripherals with an APB interface to an AXI bus. The highly con...
1840
0.0
AXI to APB Bridge IP
SmartDV’s AXI to APB Bridge IP enables seamless communication between high-performance AXI-based systems and simpler, lower-power APB peripherals. It ...
1841
0.0
AXI to APB Bus Bridge
The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction. This is accomplished via two state machines – one ...
1842
0.0
AXI to UCIe Bridge IP
SmartDV’s AXI to UCIe Bridge IP enables seamless integration between standard AMBA AXI-based SoC architectures and the emerging UCIe (Universal Chiple...
1843
0.0
AXI2APB Bridge
Truechip's AXI2APB IP provides chip designers and architects, an efficient way to connect AXI & APB based IPs with reduced latency, power, and area....
1844
0.0
AXI2APB Bridge
Truechip's AXI2APB IP provides chip designers and architects, an efficient way to connect AXI & APB based IPs with reduced latency, power, and area....
1845
0.0
AXI4 Memory Map to AXI4-Stream Bridge
Digital Blocks DB-AXI4-MM-TO-AXI4-STREAM-BRIDGE Verilog RTL IP Core accepts AXI4 Memory Map address, control, and data input, converts the address to ...
1846
0.0
CXL 1.x Controller IP
SmartDV’s CXL (Compute Express Link) 1.x Controller IP enables high-speed, low-latency, and cache-coherent communication between CPUs, memory, and acc...
1847
0.0
CXL 2.0 Retimer
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...
1848
0.0
CXL 2.x Controller IP
SmartDV’s CXL (Compute Express Link) 2.0 Controller IP extends support for advanced memory pooling, switching, and persistent memory, enhancing scalab...
1849
0.0
CXL 3.0 Device Controller
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...
1850
0.0
CXL 3.0 Dual Mode Controller
CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...
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