Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow AMBA AHB / APB/ AXI (203)
arrow CXL (21)
arrow D2D (1)
arrow Gen-Z (6)
arrow HDMI (88)
arrow I2C (96)
arrow Interlaken (3)
arrow MIL-STD-1553 (3)
arrow MIPI (508)
arrow Multi-Protocol PHY (33)
arrow PCI (241)
arrow RapidIO (6)
arrow SAS (5)
arrow SATA (74)
arrow Serdes (106)
arrow Smart Card (3)
arrow USB (405)
arrow V-by-One (22)
arrow VESA (80)
arrow Other (36)
1940 IP
351
10.0
PCIe5 Ref Clock SSCG PLL - TSMC 6FF
Analog Bits’ PCIe Gen 5 Ref Clock SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Ex...
352
10.0
HDMI 1.4b RX LINK with HDCP 1.4
Silicon Library's HDMI 1.4b RX Link IP is the best choice for our PHY IPs. HDCP 1.4 is included and customer-requested features can be added....
353
10.0
HDMI 1.4b TX LINK with HDCP 1.4
Silicon Library's HDMI 1.4b TX Link IP is the best choice for our PHY IPs. HDCP 1.4 is included and customer-requeted features can be added....
354
10.0
HDMI 2.0 RX LINK with HDCP 2.2
Silicon Library's HDMI 2.0 RX Link IP is the best choice for our PHY IPs. HDCP 2.2 is included and customer-requested features can be added....
355
10.0
HDMI 2.0 TX LINK with HDCP 2.2
Silicon Library's HDMI 2.0 TX Link IP is the best choice for our PHY IPs. HDCP 2.2 is included and customer-requested features can be added....
356
10.0
VESA DSC Encoder and Decoder IP Solutions
Synopsys VESA Display Stream Compression (DSC) Encoder and Decoder IP provides a video compression solution for up to 10K ultra-high-definition displa...
357
10.0
UFS Host Controller IP
SThe Synopsys Universal Flash Storage (UFS) Host Controller IP is a standardbased serial interface engine for implementing the JEDEC UFS interface in...
358
10.0
AHB Multi Fabric
The AHB Fabric provides the necessary infrastructure to connect up to 16 shared AHB Slaves to up to 16 AHB-Lite Bus Masters. The off-the-self configu...
359
10.0
AHB QSPI Controller with Execute in Place (XIP)
The Quad Serial Peripheral Interface (OSPI) core is a serial data link (SPI) master which controls an external serial FLASH device. Reading and wri...
360
10.0
High Performance 1-22.5G PCIe4/SAS4 PHY - TSMC 16FFC
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
361
10.0
TileLink Target
TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and other slave devices. Ti...
362
10.0
MIPI CSI-2 Receiver for FPGA
MIPI CSI-2 Rx - IP core for FPGA which based on CSI-2 standard : Camera - Application Processor....
363
10.0
MIPI D-PHY Receiver for TSMC 40nm LP
The Renesas MIPI D-PHY Receiver is useful 2 Data Channel receiver hard macro for CSI-2 of TSMC 40nm LP process....
364
10.0
MIPI D-PHY Transmitter/Receiver for Samsung 28nm FD-SOI
The Renesas MIPI D-PHY Transmitter/Receiver is useful 4 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of Samsung 28nm FD-SOI process....
365
10.0
MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP
The Renesas MIPI D-PHY Transmitter/Receiver is useful 2 Data Channel transmitter/receiver hard macro for DSI/CSI-2 of TSMC 40nm LP process....
366
10.0
MIPI D-PHY TSMC 130nm
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
367
10.0
MIPI D-PHY TSMC 28nm HPC+ @ 2.5Ghz
The Arasan’s MIPI D-PHY Analog Transceiver IP Core is fully compliant to the D-PHY specification version 1.1. It supports the MIPI® Camera Serial Inte...
368
10.0
MIPI DSI-2 Transmit Controller v1.0
The Arasan DSI-2 Device Controller IP is designed to provide MIPI DSI-2 1.0 compliant high speed serial connectivity for mobile host processors using ...
369
10.0
MIPI I3C Basic Secondary Controller
The I3C-SC core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Secondary Controller core compliant with the latest MIPI I3C Basi...
370
10.0
MIPI I3C Controller and Target fully featured IP solution
The MIPI I3C Controller IP is a highly optimized and technology-agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both ASIC and F...
371
10.0
MIPI I3C PHY I/O
Arasan’s MIPI I3CⓇ PHY I/O IP, in compliance with MIPI I3CⓇ specifications v1.1. Arasan’s MIPI I3CⓇ PHY IP is part of Arasan’s Total IP Solution for M...
372
10.0
MIPI M-PHY Designed For TSMC 28nm
ACS-AIP-MPHY-28HPM MIPI Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A...
373
10.0
MIPI M-PHY G4 Designed For TSMC 28nm HPC+
ACS-AIP-MPHY-28HPC+ MIPI Specification Version 4.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. ...
374
10.0
MIPI Soundwire PHY
The physical layer block implements all the line-side functions such as NRZI encoding & decoding, bus clash detection, data line buffer enable/disable...
375
10.0
MIPI-I3C COMBINED IP HOST/TARGET IP
The MAXVY MIPI I3C Controller IP (Host/Target) is a high-performance, standards-compliant solution for efficient multi-sensor integration in mobile,...
376
10.0
Wishbone Target
The Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a versatile design approach for semiconductor IP cores. Its go...
377
10.0
AMBA AHB Target
AMBA AHB is a bus interface designed for high-performance synthesizable applications. It specifies the interface between components such as initiator ...
378
10.0
AMBA APB Target
Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is desi...
379
10.0
AMBA AXI Target
The "advanced extensible interface" (AXI) bus is a high-performance parallel bus that connects on-chip peripheral circuits (or IP blocks) to processor...
380
10.0
ONFI 3.2 NAND Flash Controller
The Arasan ONFI 3.2 compliant NAND Flash Controller IP Core is a full featured, easy to use, synthesizable design that is easily integrated into any S...
381
10.0
UniPro 1.6 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
382
10.0
UniPro 1.8 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
383
10.0
UniPro Controller 2.0 IP (host / device)
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
384
10.0
Interlaken Controller
Interlaken is a scalable chip-to-chip protocol, which ensures the integrity of reliable data transfer and managing data flows to prevent data overload...
385
10.0
Configurable CCIX controllers for CCIX 25G supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
Synopsys’ complete CCIX IP solution consisting of controller, PHY and verification IP, delivers data transfer rates up to 32GT/s and supports cache co...
386
10.0
Configurable CCIX controllers for CCIX 32G supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
Synopsys’ complete CCIX IP solution consisting of controller, PHY and verification IP, delivers data transfer rates up to 32GT/s and supports cache c...
387
10.0
Configurable controllers for PCIe 2.0/1.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...
388
10.0
Configurable controllers for PCIe 3.1 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...
389
10.0
Configurable controllers for PCIe 4.0 and CCIX supporting Dual Mode applications
The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...
390
10.0
Configurable controllers for PCIe 4.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...
391
10.0
Configurable controllers for PCIe 5.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...
392
10.0
Configurable controllers for PCIe 6.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
The complete silicon-proven Synopsys IP solution, consisting of configurable digital controllers, PHYs, Integrity and Data Encryption (IDE) Security M...
393
10.0
Low Power PCIe2/SATA3SERDES PHY - TSMC 28HPC
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
394
10.0
Low Power PCIe3 SERDES PHY - TSMC 40G
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
395
10.0
Low Power PCIe3/SATA3 SERDES PHY - TSMC 12FFC
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
396
10.0
Low Power PCIe3/SATA3 SERDES PHY - TSMC 16FFC
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
397
10.0
Low Power PCIe3/SATA3SERDES PHY - TSMC 28HPC+
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
398
10.0
IP Solutions for the AMBA Interconnect
The Synopsys IP solutions for the ARM® AMBA® interconnect include synthesizable IP, verification IP (VIP) and automated assembly with Synopsys’ coreAs...
399
10.0
Programmable Low Power V-by-One SERDES - GLOBALFOUNDRIES 65 65G
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
400
10.0
Crossbars Interconnect
An interconnect component connects initiators and targets in a system. A single initiator system simply requires a decoder and multiplexor, which are ...